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  rej03b0127-0151 rev.1.51 jul 31, 2008 page 1 of 85 m32c/87 group (m32c/87, m32c/87a, m32c/87b) renesas mcu rej03b0127-0151 rev.1.51 jul 31, 2008 1. overview 1.1 features the m32c/87 group (m32c/87, m32c/87a, m32c/87b) is a single-chip control mcu, fabricated using high- performance silicon gate cmos technology, embedding the m32c/80 series cpu core. the m32c/87 group (m32c/ 87, m32c/87a, m32c/87b) is housed in 144-pin and 100-pin plastic molded lqfp/qfp packages. with a 16-mbyte address space, this mcu combines adva nced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. the m32c/87 group (m32c/87, m32c/87a, m32c/87b) has a multiplier and dmac adequa te for office automation, communication devices and industrial equipment, and other high-speed processing applications. 1.1.1 applications audio components, cameras, offi ce equipment, communication de vices, mobile devices, etc.
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 2 of 85 1.1.2 specifications tables 1.1 to 1.4 list the specifications of the m32c/87 group (m32c/87, m32c/87a, m32c/87b). table 1.1 specifications (144-pin package) (1/2) item function specification cpu central processing unit m32c/80 core (multiplier: 16 bits 16 bits 32 bits multiply-addition operation instructions: 16 16 + 48 48 bits) ? basic instructions: 108 ? minimum instruction execution time: 31.3 ns (f(cpu) = 32 mhz, vcc1 = 4.2 to 5.5 v) 41.7 ns (f(cpu) = 24 mhz, vcc1 = 3.0 to 5.5 v) ? operating modes: single-chip mode, memory expansion mode, and microprocessor mode memory rom, ram, data flash see tables 1.5 to 1.7 product list . power supply voltage detection vdet3 detection function, vdet4 detection function, cold start/warm start determination function external bus expansion bus/memory expansion function ? address space: 16 mbytes ? external bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 v and 5 v interfaces ? bus format: switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) clock clock generation circuits ? 4 circuits: main clock, sub clock, on-chip oscillator, pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop detectio n function ? frequency divider circuit: dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 ? low power consumption features: wait mode, stop mode interrupts ? interrupt vectors: 70 ? external interrupt inputs: 14 (nmi , int 9, key input 4) ? interrupt priority levels: 7 watchdog timer 15-bit 1 channel (with prescaler) dma dmac ? 4 channels, cycle steal method ? trigger sources: 43 ? transfer modes: 2 (single transfer and repeat transfer) dmacii ? can be activated by all peripheral function interrupt sources ? transfer modes: 2 (single transfer and burst transfer) ? immediate transfer, calculation transfer, and chain transfer functions timer timer a 16-bit timer 5 timer mode, event counter mo de, one-shot timer mode, pulse width modula tion (pwm) mode, event counter 2-phase pulse signal processing (2-phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mo de, pulse period measurement mode, pulse width measurement mode timer function for 3-phase motor control 3-phase inverter control 1 (using timer a1, timer a2, timer a4, and timer b2) on-chip dead time timer
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 3 of 85 table 1.2 specifications (144-pin package) (2/2) notes: 1. iebus is a registered trademark of nec electronics corporation. 2. available in uart0. 3. please contact a renesas sales office for optional features. item function specification serial interface uart0 to uart4 clock synchronous/asynchronous 5 i 2 c bus, special mode 2, gci mode, sim mode, irda mode (2) , iebus (optional) (1)(3) uart5, uart6 clock synchronous/asynchronous 2 a/d converter 10-bit resolution 34 channels (in single-chip mode) 10-bit resolution 18 channels (in memory expansion mode and microprocessor mode) including sample and hold function d/a converter 8-bit re solution 2 channels crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant x/y converter 16 bits x 16 bits intelligent i/o 16-bit timer 2 ? time measurement function (input capture): 8 channels ? waveform generation function (output compare): 16 channels ? communication function: clo ck synchronous mode, clock asynchronous mode, hdlc data processing mode, iebus (optional) (1)(3) ? 2-phase pulse signal processing (2-phase encoder input) 1 rom correction function address match interrupt 8 can modules supporting ca n 2.0b specification m32c/87: 16 slots 2 channels, m32c/87a: 16 slots 1 channel m32c/87b: none i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 121 with selectable pull-up resistor ? n channel open drain ports: 2 flash memory ? erase and program voltage: 3.3 v 0.3 v or 5.0 v 0.5 v ? erase and program endurance: 100 times (all areas) ? program security: rom code protect and id code check ? debug functions: on-chip debug and on-board flash reprogram operating frequency/supply voltage 32 mhz: vc c1 = 4.2 to 5.5 v, vcc2 = 3.0 v to vcc1 24 mhz: vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 v to vcc1 current consumption 32 ma (32 mhz, vcc1 = vcc2 = 5 v) 23 ma (24 mhz, vcc1 = vcc2 = 3.3 v) 45 a (approx. 1 mhz, vcc1 = vcc2 = 3.3 v, on-chip oscillator low- power consumption mode wait mode) 0.8 a (vcc1 = vcc2 = 3.3 v, stop mode) operating ambient temperature ( c) -20 to 85 c, -40 to 85 c (optional) (3) package 144-pin lqfp (plqp0144ka-a)
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 4 of 85 table 1.3 specifications (100-pin package) (1/2) item function specification cpu central processing unit m32c/80 core (multiplier: 16 bits 16 bits 32 bits multiply-addition operation instructions: 16 16 + 48 48 bits) ? basic instructions: 108 ? minimum instruction execution time: 31.3 ns (f(cpu) = 32 mhz, vcc1 = 4.2 to 5.5 v) 41.7 ns (f(cpu) = 24 mhz, vcc1 = 3.0 to 5.5 v) ? operating mode: single-chip mo de, memory expansion mode, and microprocessor mode memory rom, ram, data flash see tables 1.5 to 1.7 product list . power supply voltage detection vdet3 detection function, vdet4 detection function, cold start/warm start determination function external bus expansion bus/memory expansion function ? address space: 16 mbytes ? external bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 v and 5 v interfaces ? bus format: switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) clock clock generation circuits ? 4 circuits: main clock, sub clock, on-chip oscillator, pll frequency synthesizer ? oscillation stop detection: main clock oscillation stop detectio n function ? frequency divider circuit: dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 ? low power consumption features: wait mode, stop mode interrupts ? interrupt vectors: 70 ? external interrupt inputs: 11 (nmi , int 6, key input 4) ? interrupt priority levels: 7 watchdog timer 15-bit 1 channel (with prescaler) dma dmac ? 4 channels, cycle steal method ? trigger sources: 43 ? transfer modes: 2 (single transfer and repeat transfer) dmacii ? can be activated by all peripheral function interrupt sources ? transfer modes: 2 (single transfer and burst transfer) ? immediate transfer, calculation transfer, and chain transfer functions timer timer a 16-bit timer 5 timer mode, event counter mo de, one-shot timer mode, pulse width modula tion (pwm) mode, event counter 2-phase pulse signal processing (2-phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mo de, pulse period measurement mode, pulse width measurement mode timer function for 3-phase motor control 3-phase inverter control 1 (using timer a1, timer a2, timer a4, and timer b2) on-chip dead time timer
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 5 of 85 table 1.4 specifications (100-pin package) (2/2) notes: 1. iebus is a registered trademark of nec electronics corporation. 2. available in uart0. 3. please contact a renesas sales office for optional features. item function specification serial interface uart0 to uart4 clock synchronous/asynchronous 5 i 2 c bus, special mode 2, gci mode, sim mode, irda mode (2) , iebus (optional) (1)(3) uart5 clock synchronous/asynchronous 1 a/d converter 10-bit resolution 26 channels (in single-chip mode) 10-bit resolution 10 channels (in memory expansion mode and microprocessor mode) including sample and hold function d/a converter 8-bit re solution 2 channels crc calculation circuit crc-ccitt (x 16 + x 12 + x 5 + 1) compliant x/y converter 16 bits x 16 bits intelligent i/o 16-bit timer 2 ? time measurement function (input capture): 8 channels ? waveform generation function (output compare): 10 channels ? communication function: clo ck synchronous mode, clock asynchronous mode, hdlc data processing mode, iebus (optional) (1)(3) ? 2-phase pulse signal processing (2-phase encoder input) 1 rom correction function address match interrupt 8 can modules supporting ca n 2.0b specification m32c/87: 16 slots 2 channels, m32c/87a: 16 slots 1 channel m32c/87b: none i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 85, select able pull-up resistor ? n channel open drain ports: 2 flash memory ? erase and program voltage: 3.3 v 0.3 v or 5.0 v 0.5 v ? erase and program endurance: 100 times (all areas) ? program security: rom code protect and id code check ? debug functions: on-chip debug and on-board flash reprogram operating frequency/supply voltage 32 mhz: vc c1 = 4.2 to 5.5 v, vcc2 = 3.0 v to vcc1 24 mhz: vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 v to vcc1 current consumption 32 ma (32 mhz, vcc1 = vcc2 = 5 v) 23 ma (24 mhz, vcc1 = vcc2 = 3.3 v) 45 a (approx. 1 mhz, vcc1 = vcc2 = 3.3 v, on-chip oscillator low- power consumption mode wait mode) 0.8 a (vcc1 = vcc2 = 3.3 v, stop mode) operating ambient temperature ( c) -20 to 85 c, -40 to 85 c (optional) (3) package 100-pin lqfp (plqp0100kb-a) 100-pin qfp (prqp0100jb-a)
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 6 of 85 1.2 product list tables 1.5 to 1.7 list product information. figure 1.1 shows product numbering system. table 1.5 m32c/87 group (1) (m32c/87: 2-channel can module) current as of jul. 2008 note: 1. additional 4-kbyte space is available for data flash memory. table 1.6 m32c/87 group (2) (m32c/87a: 1-channel can module) current as of jul. 2008 note: 1. additional 4-kbyte space is available for data flash memory. part number package code rom capacity ram capacity remarks m3087bflgp plqp0144ka-a (144p6q-a) 1 mb + 4 kb (1) 48 kb flash memory m30879flfp prqp0100jb-a (100p6s-a) m30879flgp plqp0100kb-a (100p6q-a) m3087bfkgp plqp0144ka-a (144p6q-a) 768 kb + 4 kb (1) m30879fkgp plqp0100kb-a (100p6q-a) m30878fjgp plqp0144ka-a (144p6q-a) 512 kb + 4 kb (1) 31 kb m30876fjgp plqp0100kb-a (100p6q-a) m30875fhgp plqp0144ka-a (144p6q-a) 384 kb + 4 kb (1) 24 kb m30873fhgp plqp0100kb-a (100p6q-a) m30878mj-xxxgp plqp0144ka-a (144p6q-a) 512 kb 31 kb mask rom m30876mj-xxxfp prqp0100jb-a (100p6s-a) m30876mj-xxxgp plqp0100kb-a (100p6q-a) m30875mh-xxxgp plqp0144ka-a (144p6q-a) 384 kb 24 kb m30873mh-xxxgp plqp0100kb-a (100p6q-a) part number package code rom capacity ram capacity remarks m3087bflagp plqp0144ka-a (144p6q-a) 1 mb + 4 kb (1) 48 kb flash memory m30879flafp prqp0100jb-a (100p6s-a) m30879flagp plqp0100kb-a (100p6q-a) m3087bfkagp plqp0144ka-a (144p6q-a) 768 kb + 4 kb (1) m30879fkagp plqp0100kb-a (100p6q-a) m30878fjagp plqp0144ka-a (144p6q-a) 512 kb + 4 kb (1) 31 kb m30876fjagp plqp0100kb-a (100p6q-a) m30875fhagp plqp0144ka-a (144p6q-a) 384 kb + 4 kb (1) 24 kb m30873fhagp plqp0100kb-a (100p6q-a) M30878MJA-XXXGP plqp0144ka-a (144p6q-a) 512 kb 31 kb mask rom m30876mja-xxxfp prqp0100jb-a (100p6s-a) m30876mja-xxxgp plqp0100kb-a (100p6q-a) m30875mha-xxxgp plqp0144ka-a (144p6q-a) 384 kb 24 kb m30873mha-xxxgp plqp0100kb-a (100p6q-a)
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 7 of 85 table 1.7 m32c/87 group (3) (m32c/87b: no can module) current as of jul. 2008 note: 1. additional 4-kbyte space is available for data flash memory. figure 1.1 product numbering system part number package code rom capacity ram capacity remarks m3087bflbgp plqp0144ka-a (144p6q-a) 1 mb + 4 kb (1) 48 kb flash memory m30879flbfp prqp0100jb-a (100p6s-a) m30879flbgp plqp0100kb-a (100p6q-a) m3087bfkbgp plqp0144ka-a (144p6q-a) 768 kb + 4 kb (1) m30879fkbgp plqp0100kb-a (100p6q-a) m30878fjbgp plqp0144ka-a (144p6q-a) 512 kb + 4 kb (1) 31 kb m30876fjbgp plqp0100kb-a (100p6q-a) m30875fhbgp plqp0144ka-a (144p6q-a) 384 kb + 4 kb (1) 24 kb m30873fhbgp plqp0100kb-a (100p6q-a) m30878mjb-xxxgp plqp0144ka-a (144p6q-a) 512 kb 31 kb mask rom m30876mjb-xxxfp prqp0100jb-a (100p6s-a) m30876mjb-xxxgp plqp0100kb-a (100p6q-a) m30875mhb-xxxgp plqp0144ka-a (144p6q-a) 384 kb 24 kb m30873mhb-xxxgp plqp0100kb-a (100p6q-a) m30 87 6 m j -xxx gp package type option fp: prqp0100jb-a (100p6s-a) gp: plqp0144ka-a (144p6q-a) plqp0100kb-a (100p6q-a) rom number: omitted for the flash memory version classification blank: m32c/87 a: m32c/87a b: m32c/87b rom capacity h: 384 kbytes j: 512 kbytes k: 768 kbytes l: 1024 kbytes memory type m: mask rom version f: flash memory version ram capacity, pin count, etc (the value itself has no specific meaning.) m32c/87 group m16c family part no.
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 8 of 85 1.3 block diagram figure 1.2 shows a block diagram of the m32c/87 group (m32c/87, m32c/87a, m32c/87b). figure 1.2 m32c/87 group (m32c/87, m32c/87a, m32c/87b) block diagram port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 internal peripheral functions three-phase motor control circuit watchdog timer (15 bits) 8-bit d/a converters: 2 circuits intelligent i/o time measurement function: 8 channels waveform generation function: 16 channels (4) communication function: clock synchronous serial interface, uart, hdlc data processing, iebus can modules:2 channels (5) serial interface: 7 channels (3) x/y converter: 16 bits x 16 bits crc calculation circuit (ccitt): x 16 + x 12 + x 5 + 1 clock generation circuits: xin-xout xcin-xcout on-chip oscillator pll frequency synthesizer dmac: 4 channels dmacii 10-bit a/d converter: 1 circuit 34 channels for input (2) port p13 (1) port p12 (1) port p11 (1) port p15 (1) port p14 (1) port p10 port p9 port p8 p8_5 timers (16 bits) output (timer a): 5 input (timer b): 6 notes: 1. ports p11 to p15 are provided in the 144-pin package only. 2. 34 channels are available in the 144-pin packa ge. 26 channels are available in the 100-pin package. 3. 6 channels are available in the 100-pin package. 4. 10 channels are available in the 100-pin package. 5. m32c/87a has 1 channel. m32c/87b has no can module. 8 8 8 8 8 8 8 8 8 rom memory multiplier m32c/80 series cpu core flg isp intb usp pc svf svp vct sb fb r3 a1 a0 r2 r1h r1l r1h r1l r1h r1l r0h r0l 8 5 8 7 8 8 7 ram
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 9 of 85 1.4 pin assignments 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 m32c/87 group (m32c/87, m32c/87a, m32c/87b) plqp0144ka-a (144p6q-a) (top view) d8 / p1_0 d7 / an0_7 / p0_7 d6 / an0_6 / p0_6 d5 / an0_5 / p0_5 d4 / an0_4 / p0_4 p11_4 outc1_3 / inpc1_3 / p11_3 isrxd1 / outc1_2 / inpc1_2 / p11_2 isclk1 / outc1_1 / inpc1_1 / p11_1 istxd1 / outc1_0 / inpc1_0 / p11_0 d3 / an0_3 / p0_3 d2 / an0_2 / p0_2 d1 / an0_1 / p0_1 d0 / an0_0 / p0_0 an15_7 / rts6 / cts6 / p15_7 an15_6 / clk6 / p15_6 an15_5 / rxd6 / p15_5 an15_4 / txd6 / p15_4 an15_3 / rts5 / cts5 / p15_3 an15_2 / isrxd0 / rxd5 / p15_2 an15_1 / isclk0 / clk5 / p15_1 an15_0 / istxd0 / txd5 / p15_0 vss vcc1 an_7 / rtp3_3 / ki3 / p10_7 an_6 / rtp3_2 / ki2 / p10_6 an_5 / rtp3_1 / ki1 / p10_5 an_3 / rtp1_3 / p10_3 an_2 / rtp1_2 / p10_2 an_1 / rtp1_1 / p10_1 an_0 / rtp1_0 / p10_0 avss avcc vref adtrg / stxd4 / scl4 / rxd4 / p9_7 (5) anex1 / srxd4 / sda4 / txd4 / can1out / p9_6 (5) anex0 / can1wu / can1in / clk4 / p9_5 da1 / ss4 / rts4 / cts4 / tb4in / p9_4 da0 / ss3 / rts3 / cts3 / tb3in / p9_3 istxd2 / ieout / outc2_0 / srxd3 / sda3 / txd3 / tb2in / p9_2 isrxd2 / iein / stxd3 / scl3 / rxd3 / tb1in / p9_1 clk3 / tb0in / p9_0 int8 / p14_6 int7 / p14_5 int6 / p14_4 outc1_7 / inpc1_7 / p14_3 outc1_6 / inpc1_6 / p14_2 outc1_5 / inpc1_5 / p14_1 outc1_4 / inpc1_4 / p14_0 byte cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc1 nmi / p8_5 int2 / p8_4 (5) can1in / can0in / int1 / p8_3 (5) can1out / can0out / int0 / p8_2 outc1_5 / inpc1_5 / rts5 / cts5 / rtp2_3 / u / ta4in / p8_1 isrxd0 / rxd5 / u / ta4out / p8_0 isclk0 / outc1_4 / inpc1_4 / can0in / clk5 / rtp2_2 / ta3in / p7_7 istxd0 / outc1_3 / inpc1_3 / txd5 / can0out / ta3out / p7_6 isrxd0 / outc1_2 / inpc1_2 / rtp2_1 / w / ta2in / p7_5 isclk1 / outc1_1 / inpc1_1 / rtp2_0 / w / ta2out / p7_4 i s t x d 1 / o u t c 1 _ 0 / i n p c 1 _ 0 / s s 2 / r t s 2 / c t s 2 / v / t a 1 i n / p 7 _ 3 clk2 / v / ta1out / p7_2 (1) (4) p7_1 p4_3 / a19 vcc2 p4_2 / a18 p4_1 / a17 p4_0 / a16 vss p3_7 / a15, [a15/d15] p3_6/ a14, [a14/d14] p3_5/ a13, [a13/d13] p3_4 / a12, [a12/d12] p3_3 / a11, [a11/d11] p3_2 / a10, [a10/d10] p 3 _ 1 / a 9 , [ a 9 / d 9 ] p3_0/ a8, [a 8/d8] (7) p 2 _ 7 / a n 2 _ 7 / a 7 , [ a 7 / d 7 ] p 2 _ 6 / a n 2 _ 6 / a 6 , [ a 6 / d 6 ] p 2 _ 5 / a n 2 _ 5 / a 5 , [ a 5 / d 5 ] p 2 _ 4 / a n 2 _ 4 / a 4 , [ a 4 / d 4 ] v s s v c c 2 p 1 2 _ 0 / t x d 6 p 1 2 _ 1 / c l k 6 p 1 2 _ 2 / r x d 6 p 1 2 _ 3 / c t s 6 / r t s 6 p 1 2 _ 4 p 2 _ 3 / a n 2 _ 3 / a 3 , [ a 3 / d 3 ] p 2 _ 2 / a n 2 _ 2 / a 2 , [ a 2 / d 2 ] p 2 _ 1 / a n 2 _ 1 / a 1 , [ a 1 / d 1 ] p 2 _ 0 / a n 2 _ 0 / a 0 , [ a 0 / d 0 ] p 1 _ 1 / d 9 p 1 _ 2 / d 1 0 p 1 _ 3 / d 1 1 p 1 _ 4 / d 1 2 p 1 _ 5 / i n t 3 / d 1 3 p 1 _ 6 / i n t 4 / d 1 4 p 1 _ 7 / i n t 5 / d 1 5 p7_0 (2) (4) p6_7 / txd1 / sda1 / srxd1 vcc1 p6_6 / rxd1 / scl1 / stxd1 vss p6_5 / clk1 p6_4 (3) p6_3 / txd0 / sda0 / srxd0 / irdaout p6_2 / rxd0 / scl0 / stxd0 / irdain p6_1 / rtp0_1 / clk0 p6_0 / rtp0_0 / cts0 / rts0 / ss0 p13_7 / outc2_7 p13_6 / outc2_1 / isclk2 p13_5 / outc2_2 / isrxd2 / iein p13_4 / outc2_0 / istxd2 / ieout p5_7 / rdy p5_6 / ale p5_5 / hold p5_4 / hlda / ale p13_3 / outc2_3 vss p13_2 / outc2_6 vcc2 p13_1 / outc2_5 p13_0 / outc2_4 p5_3 / clkout / bclk / ale p5_2 / rd p5_1 / wrh / bhe p5_0 / wrl / wr p12_7 p12_6 p12_5 p4_7 / cs0 / a23 p4_6 / cs1 / a22 p4_5 / cs2 / a21 p4_4 / cs3 / a20 an_4 / rtp3_0 / ki0 / p10_4 notes: 1. p7_1 / ta0in / tb5in / rtp0_3 / rxd2 / scl2 / stxd2 / inpc1_7 / outc1_7 / outc2_2 / isrxd2 / iein 2. p7_0 / ta0out / rtp0_2 / txd2 / sda2 / srxd2 / inpc1_6 / outc1_6 / outc2_0 / istxd2 / ieout 3. p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 4. p7_0 and p7_1 are n-channel open drain output ports. 5. the can pins cannot be used in m32c/87b. only can0 pins can be used in m32c/87a. 6. refer to package dimensions for the pin1 position on the package. 7. pin names in brackets [ ] represent a single functional signal. they should not be considered as two separate functiona l signals. (note 6) ( note 7) ( note 7) figures 1.3 to 1.5 show pin assignments (top view). figure 1.3 pin assignment for 144-pin package
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 10 of 85 table 1.8 144-pin package list of pin names (1/4) note: 1. the can pins cannot be used in m32c/87b . only can0 pins can be used in m32c/87a . pin no. control pin port interrupt pin timer pin uart/can pin (1) intelligent i/o pin analog pin bus control pin 1 p9_6 txd4/sda4/srxd4/ can1out anex1 2 p9_5 clk4/can1in/can1wu anex0 3 p9_4 tb4in cts4 /rts4 /ss4 da1 4 p9_3 tb3in cts3 /rts3 /ss3 da0 5 p9_2 tb2in txd3/sda3/srxd3 outc2_0/ieout/istxd2 6 p9_1 tb1in rxd3/scl3/stxd3 iein/isrxd2 7 p9_0 tb0in clk3 8 p14_6 int8 9 p14_5 int7 10 p14_4 int6 11 p14_3 inpc1_7/outc1_7 12 p14_2 inpc1_6/outc1_6 13 p14_1 inpc1_5/outc1_5 14 p14_0 inpc1_4/outc1_4 15 byte 16 cnvss 17 xcin p8_7 18 xcout p8_6 19 reset 20 xout 21 vss 22 xin 23 vcc1 24 p8_5 nmi 25 p8_4 int2 26 p8_3 int1 can0in/can1in 27 p8_2 int0 can0out/can1out 28 p8_1 ta4in/u /rtp2_3 cts5 /rts5 inpc1_5/outc1_5 29 p8_0 ta4out/u rxd5 isrxd0 30 p7_7 ta3in/rtp2_2 clk5/can0in inpc1_4/outc1_4/ isclk0 31 p7_6 ta3out txd5/can0out inpc1_3/outc1_3/ istxd0 32 p7_5 ta2in/w /rtp2_1 inpc1_2/outc1_2/ isrxd1 33 p7_4 ta2out/w/ rtp2_0 inpc1_1/outc1_1/ isclk1 34 p7_3 ta1in/v cts2 /rts2 /ss2 inpc1_0/outc1_0/ istxd1 35 p7_2 ta1out/v clk2 36 p7_1 ta0in/tb5in/ rtp0_3 rxd2/scl2/stxd2 inpc1_7/outc1_7/ outc2_2/isrxd2/iein 37 p7_0 ta0out/rtp0_2 txd2/sda2/srxd2 inpc1_6/outc1_6/ outc2_0/istxd2/ieout 38 p6_7 txd1/sda1/srxd1 39 vcc1 40 p6_6 rxd1/scl1/stxd1
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 11 of 85 table 1.9 144-pin package list of pin names (2/4) pin no. control pin port interrupt pin timer pin uart/can pin intelligent i/o pin analog pin bus control pin 41 vss 42 p6_5 clk1 43 p6_4 cts1 /rts1 /ss1 outc2_1/isclk2 44 p6_3 txd0/sda0/srxd0/ irdaout 45 p6_2 rxd0/scl0/stxd0/ irdain 46 p6_1 rtp0_1 clk0 47 p6_0 rtp0_0 cts0 /rts0 /ss0 48 p13_7 outc2_7 49 p13_6 outc2_1/isclk2 50 p13_5 outc2_2/isrxd2/ iein 51 p13_4 outc2_0/istxd2/ ieout 52 p5_7 rdy 53 p5_6 ale 54 p5_5 hold 55 p5_4 hlda /ale 56 p13_3 outc2_3 57 vss 58 p13_2 outc2_6 59 vcc2 60 p13_1 outc2_5 61 p13_0 outc2_4 62 clkout p5_3 bclk/ale 63 p5_2 rd 64 p5_1 wrh /bhe 65 p5_0 wrl /wr 66 p12_7 67 p12_6 68 p12_5 69 p4_7 cs0 /a23 70 p4_6 cs1 /a22 71 p4_5 cs2 /a21 72 p4_4 cs3 /a20 73 p4_3 a19 74 vcc2 75 p4_2 a18 76 vss 77 p4_1 a17 78 p4_0 a16 79 p3_7 a15,[a15/d15] 80 p3_6 a14,[a14/d14]
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 12 of 85 table 1.10 144-pin package list of pin names (3/4) pin no. control pin port interrupt pin timer pin uart/can pin intelligent i/o pin analog pin bus control pin 81 p3_5 a13,[a13/d13] 82 p3_4 a12,[a12/d12] 83 p3_3 a11,[a11/d11] 84 p3_2 a10,[a10/d10] 85 p3_1 a9,[a9/d9] 86 p12_4 87 p12_3 cts6 /rts6 88 p12_2 rxd6 89 p12_1 clk6 90 p12_0 txd6 91 vcc2 92 p3_0 a8,[a8/d8] 93 vss 94 p2_7 an2_7 a7,[a7/d7] 95 p2_6 an2_6 a6,[a6/d6] 96 p2_5 an2_5 a5,[a5/d5] 97 p2_4 an2_4 a4,[a4/d4] 98 p2_3 an2_3 a3,[a3/d3] 99 p2_2 an2_2 a2,[a2/d2] 100 p2_1 an2_1 a1,[a1/d1] 101 p2_0 an2_0 a0,[a0/d0] 102 p1_7 int5 d15 103 p1_6 int4 d14 104 p1_5 int3 d13 105 p1_4 d12 106 p1_3 d11 107 p1_2 d10 108 p1_1 d9 109 p1_0 d8 110 p0_7 an0_7 d7 111 p0_6 an0_6 d6 112 p0_5 an0_5 d5 113 p0_4 an0_4 d4 114 p11_4 115 p11_3 inpc1_3/outc1_3 116 p11_2 inpc1_2/outc1_2/ isrxd1 117 p11_1 inpc1_1/outc1_1/ isclk1 118 p11_0 inpc1_0/outc1_0/ istxd1 119 p0_3 an0_3 d3 120 p0_2 an0_2 d2
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 13 of 85 table 1.11 144-pin package list of pin names (4/4) pin no. control pin port interrupt pin timer pin uart/can pin intelligent i/o pin analog pin bus control pin 121 p0_1 an0_1 d1 122 p0_0 an0_0 d0 123 p15_7 cts6 /rts6 an15_7 124 p15_6 clk6 an15_6 125 p15_5 rxd6 an15_5 126 p15_4 txd6 an15_4 127 p15_3 cts5 /rts5 an15_3 128 p15_2 rxd5 isrxd0 an15_2 129 p15_1 clk5 isclk0 an15_1 130 vss 131 p15_0 txd5 istxd0 an15_0 132 vcc1 133 p10_7 ki3 rtp3_3 an_7 134 p10_6 ki2 rtp3_2 an_6 135 p10_5 ki1 rtp3_1 an_5 136 p10_4 ki0 rtp3_0 an_4 137 p10_3 rtp1_3 an_3 138 p10_2 rtp1_2 an_2 139 p10_1 rtp1_1 an_1 140 avss 141 p10_0 rtp1_0 an_0 142 vref 143 avcc 144 p9_7 rxd4/scl4/stxd4 adtrg
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 14 of 85 figure 1.4 pin assignment for 100-pin package 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 m32c/87 group (m32c/87,m32c/87a,m32c/87b) prqp0100jb-a (100p6s-a) (top view) p1_0 / d8 d7 / an0_7 / p0_7 d6 / an0_6 / p0_6 d5 / an0_5 / p0_5 d4 / an0_4 / p0_4 d3 / an0_3 / p0_3 d2 / an0_2 / p0_2 d1 / an0_1 / p0_1 d0 / an0_0 / p0_0 an_7 / rtp3_3 / ki3 / p10_7 an_6 / rtp3_2 / ki2 / p10_6 an_5 / rtp3_1 / ki1 / p10_5 an_4 / rtp3_0 / ki0 / p10_4 an_3 / rtp1_3 / p10_3 an_2 / rtp1_2 / p10_2 an_1 / rtp1_1 / p10_1 an_0 / rtp1_0 / p10_0 avss avcc vref adtrg / stxd4 / scl4 / rxd4 / p9_7 da1 / ss4 / rts4 / cts4 / tb4in / p9_4 da0 / ss3 / rts3 / cts3 / tb3in / p9_3 istxd2 / ieout / outc2_0 / srxd3 / sda3 / txd3 / tb2in / p9_2 isrxd2 / iein / stxd3 / scl3 / rxd3 / tb1in / p9_1 clk3 / tb0in / p9_0 byte cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc1 nmi / p8_5 int2 / p8_4 (4) can1in / can0in / int1 / p8_3 (4) can1out / can0out / int0 / p8_2 outc1_5 / inpc1_5 / rts5 / cts5 / rtp2_3 / u / ta4in / p8_1 isrxd0 / rxd5 / u / ta4out / p8_0 (4) isclk0 / outc1_4 / inpc1_4 / can0in / clk5 / rtp2_2 / ta3in / p7_7 (4) istxd0 / outc1_3 / inpc1_3 / can0out / txd5 / ta3out / p7_6 isrxd1 / outc1_2 / inpc1_2 / rtp2_1 / w / ta2in / p7_5 isclk1 / outc1_1 / inpc1_1 / rtp2_0 / w / ta2out / p7_4 istxd1 / outc1_0 / inpc1_0 / ss2 / rts2 / cts2 / v / ta1in / p7_3 p1_1 / d9 p 1 _ 2 / d 1 0 p1_3 / d11 (4) anex1 / can1out / srxd4 / sda4 / txd4 / p9_6 (4) anex0 / can1wu / can1in / clk4 / p9_5 notes: 1. p7_1 / ta0in / tb5in / rtp0_3 / rxd2 / scl2 / stxd2 / inpc1_7 / outc1_7 / outc2_2 / isrxd2 / iein 2. p7_0 / ta0out / rtp0_2 / txd2 / sda2 / srxd2 / inpc1_6 / outc1_6 / outc2_0 / istxd2 / ieout 3. p7_0 and p7_1 are n-channel open drain output ports. 4. the can pins cannot be used in m32c/87b. only can0 pins can be used in m32c/87a. 5. refer to package dimensions for the pin1 position on the package. 6. pin names in brackets [ ] represent a single functional signal. they should not be considered as two separate functiona l signals. clk2 / v / ta1out / p7_2 (1)(3) p7_1 (2)(3) p7_0 p6_7 /txd1 / sda1 / srxd1 p6_6 / rxd1 / scl1 / stxd1 p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 p6_3 / txd0 / sda0 / srxd0 / irdaout p6_2 / rxd0 / scl0 / stxd0 / irdain p6_1 / rtp0_1 / clk0 p6_0 / rtp0_1 / cts0 / rts0 / ss0 p5_7 / rdy p5_6 / ale p5_5 / hold p5_4 / hlda / ale p5_3 / clkout / bclk / ale p5_2 / rd p5_1 / wrh / bhe p5_0 / wrl / wr p4_7 / cs0 / a23 p4_6 / cs1 / a22 p4_5 / cs2 / a21 p4_4 / cs3 / a20 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p4_3 / a19 p4_2 / a18 26 27 28 29 30 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 p4_1 / a17 p4_0 / a16 p3_7 / a15, [a15/d15] p3_6 / a14, [a14/d14] p3_5 / a13, [a13/d13] p3_4 / a12, [a12/d12] p3_3 / a11, [a11/d11] p3_2 / a10, [a10/d10] p3_1 / a9, [a9/d9] p3_0 / a8, [a8/d8] (6) p2_7 / an2_7 / a7, [a7/d7] p2_6 / an2_6 / a6, [a6/d6] p2_5 / an2_5 / a5, [a5/d5] p2_4 / an2_4 / a4, [a4/d4] vss vcc2 p2_3 / an2_3 / a3, [a3/d3] p2_2 / an2_2 / a2, [a2/d2] p2_1 / an2_1 / a1, [a1/d1] p2_0 / an2_0 / a0, [a0/d0] p1_4 / d12 p1_5 / int3 / d13 p1_6 / int4 / d14 p1_7 / int5 / d15 ( note 6) ( note 6) ( note 5)
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 15 of 85 figure 1.5 pin assignment for 100-pin package 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 m32c/87 group (m32c/87,m32c/87a,m32c/87b) plqp0100kb-a (100p6q-a) (top view) d8 / p1_0 d7 / an0_7 / p0_7 d6 / an0_6 / p0_6 d5 / an0_5 / p0_5 d4 / an0_4 / p0_4 d3 / an0_3 / p0_3 d2 / an0_2 / p0_2 d1 / an0_1 / p0_1 d0 / an0_0 / p0_0 an_7 / rtp3_3 / ki3 / p10_7 an_6 / rtp3_2 / ki2 / p10_6 an_5 / rtp3_1 / ki1 / p10_5 an_4 / rtp3_0 / ki0 / p10_4 an_3 / rtp1_3 p10_3 an_2 / rtp1_2 / p10_2 an_1 / rtp1_1 / p10_1 an_0 / rtp1_0 / p10_0 avss avcc vref adtrg / stxd4 / scl4 / rxd4 / p9_7 da1 / ss4 / rts4 / cts4 / tb4in / p9_4 da0 / ss3 / rts3 / cts3 / tb3in / p9_3 istxd2 / ieout / outc2_0 / srxd3 / sda3 / txd3 / tb2in / p9_2 isrxd2 / iein / stxd3 / scl3 / rxd3 / tb1in / p9_1 clk3 / tb0in / p9_0 byte cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc1 nmi / p8_5 int2 / p8_4 (4) can1in / can0in / int1 / p8_3 (4) can1out / can0out / int0 / p8_2 outc1_5 / inpc1_5 / rts5 / cts5 / rtp2_3 / u / ta4in / p8_1 isrxd0 / rxd5 / u / ta4out / p8_0 (4) isclk0 / outc1_4 / inpc1_4 / can0in / clk5 / rtp2_2 / ta3in / p7_7 (4) istxd0 / outc13 / inpc13 / can0out / txd5 / ta3out / p7_6 isrxd1 / outc1_2 / inpc1_2 / rtp2_1 / w / ta2in / p7_5 isclk1 / outc1_1 / inpc1_1 / rtp2_0 / w / ta2out / p7_4 istxd1 / outc1_0 / inpc1_0 / ss2 / rts2 / cts2 / v / ta1in / p7_3 p7_2 / ta1out / v / clk2 p7_1 (1)(3) p4_1 / a17 p4_0 / a16 p3_7 / a15, [a15/d15] p3_6 / a14, [a14/d14] p3_5 / a13, [a13/d13] p3_4 / a12, [a12/d12] p3_3 / a11, [a11/d11] p3_2 / a10, [a10/d10] p3_1 / a9, [a9/d9] p3_0 / a8, [a8/d8] (6) p2_7 / an2_7 / a7, [a7/d7] p2_6 / an2_6 / a6, [a6/d6] p2_5 / an2_5 / a5, [a5/d5] p2_4 / an2_4 / a4, [a4/d4] vss vcc2 p2_3 / an2_3 / a3, [a3/d3] p2_2 / an2_2 / a2, [a2/d2] p2_1 / an2_1 / a1, [a1/d1] p2_0 / an2_0 / a0, [a0/d0] d9 / p1_1 d 1 0 / p 1 _ 2 p1_3 / d11 p1_4 / d12 p1_5 / int3 / d13 p1_6 / int4 / d14 p1_7 / int5 / d15 p7_0 (2)(3) p6_7 /txd1 / sda1 / srxd1 p6_6 / rxd1 / scl1 / stxd1 p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 p6_3 / txd0 / sda0 / srxd0 / irdaout p6_2 / rxd0 / scl0 / stxd0 / irdain p6_1 / rtp0_1 / clk0 p6_0 / rtp0_0 / cts0 / rts0 / ss0 p5_7 / rdy p5_6 / ale p5_5 / hold p5_4 / hlda / ale p5_3 / clkout / bclk / ale p5_2 / rd p5_1 / wrh / bhe p5_0 / wrl / wr p4_7 / cs0 / a23 p4_6 / cs1 / a22 p4_5 / cs2 / a21 p4_4 / cs3 / a20 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 (4) anex1 / can1out / srxd4 / sda4 / txd4 / p9_6 (4) anex0 / can1wu / can1in / clk4 / p9_5 26 27 28 29 30 p4_3 / a19 p4_2 / a18 notes: 1. p7_1 / ta0in / tb5in / rtp0_3 / rxd2 / scl2 / stxd2 / inpc1_7 / outc1_7 / outc2_2 / isrxd2 / iein 2. p7_0 / ta0out / rtp0_2 / txd2 / sda2 / srxd2 / inpc1_6 / outc1_6 / outc2_0 / istxd2 / ieout 3. p7_0 and p7_1 are n-channel open drain output ports. 4. the can pins cannot be used in m32c/87b. only can0 pins can be used in m32c/87a. 5. refer to package dimensions for the pin1 position on the package. 6. pin names in brackets [ ] represent a single functional signal . they should not be considered as two separate functional sig nals. ( note 6) ( note 6) ( note 5)
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 16 of 85 table 1.12 100-pin package list of pin names (1/3) note: 1. the can pins cannot be used in m32c/87b . only can0 pins can be used in m32c/87a . pin no. control pin port interrupt pin timer pin uart/can pin (1) intelligent i/o pin analog pin bus control pin fp gp 1 99 p9_6 txd4/sda4/srxd4/ can1out anex1 2 100 p9_5 clk4/can1in/ can1wu anex0 3 1 p9_4 tb4in cts4 /rts4 /ss4 da1 4 2 p9_3 tb3in cts3 /rts3 /ss3 da0 5 3 p9_2 tb2in txd3/sda3/srxd3 outc2_0/ieout/istxd2 6 4 p9_1 tb1in rxd3/scl3/stxd3 iein/isrxd2 7 5 p9_0 tb0in clk3 8 6 byte 9 7 cnvss 10 8 xcin p8_7 11 9 xcout p8_6 12 10 reset 13 11 xout 14 12 vss 15 13 xin 16 14 vcc1 17 15 p8_5 nmi 18 16 p8_4 int2 19 17 p8_3 int1 can0in/can1in 20 18 p8_2 int0 can0out/can1out 21 19 p8_1 ta4in/u /rtp2_3 cts5 /rts5 inpc1_5/outc1_5 22 20 p8_0 ta4out/u rxd5 isrxd0 23 21 p7_7 ta3in/rtp2_2 clk5/can0in inpc1_4/outc1_4/ isclk0 24 22 p7_6 ta3out txd5/can0out inpc1_3/outc1_3/ istxd0 25 23 p7_5 ta2in/w /rtp2_1 inpc1_2/outc1_2 isrxd1 26 24 p7_4 ta2out/w/ rtp2_0 inpc1_1/outc1_1/ isclk1 27 25 p7_3 ta1in/v cts2 /rts2 /ss2 inpc1_0/outc1_0/ istxd1 28 26 p7_2 ta1out/v clk2 29 27 p7_1 ta0in/tb5in/ rtp0_3 rxd2/scl2/stxd2 inpc1_7/outc1_7/ outc2_2/isrxd2/iein 30 28 p7_0 ta0out/rtp0_2 txd2/sda2/srxd2 inpc1_6/outc1_6/ outc2_0/istxd2/ieout 31 29 p6_7 txd1/sda1/srxd1 32 30 p6_6 rxd1/scl1/stxd1 33 31 p6_5 clk1 34 32 p6_4 cts1 /rts1 /ss1 outc2_1/isclk2 35 33 p6_3 txd0/sda0/srxd0/ irdaout 36 34 p6_2 rxd0/scl0/stxd0/ irdain 37 35 p6_1 rtp0_1 clk0 38 36 p6_0 rtp0_0 cts0 /rts0 /ss0 39 37 p5_7 rdy 40 38 p5_6 ale
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 17 of 85 table 1.13 100-pin package list of pin names (2/3) pin no. control pin port interrupt pin timer pin uart/can pin intelligent i/o pin analog pin bus control pin fp gp 41 39 p5_5 hold 42 40 p5_4 hlda /ale 43 41 clkout p5_3 bclk/ale 44 42 p5_2 rd 45 43 p5_1 wrh /bhe 46 44 p5_0 wrl /wr 47 45 p4_7 cs0 /a23 48 46 p4_6 cs1 /a22 49 47 p4_5 cs2 /a21 50 48 p4_4 cs3 /a20 51 49 p4_3 a19 52 50 p4_2 a18 53 51 p4_1 a17 54 52 p4_0 a16 55 53 p3_7 a15,[a15/d15] 56 54 p3_6 a14,[a14/d14] 57 55 p3_5 a13,[a13/d13] 58 56 p3_4 a12,[a12/d12] 59 57 p3_3 a11,[a11/d11] 60 58 p3_2 a10,[a10/d10] 61 59 p3_1 a9,[a9/d9] 62 60 vcc2 63 61 p3_0 a8,[a8/d8] 64 62 vss 65 63 p2_7 an2_7 a7,[a7/d7] 66 64 p2_6 an2_6 a6,[a6/d6] 67 65 p2_5 an2_5 a5,[a5/d5] 68 66 p2_4 an2_4 a4,[a4/d4] 69 67 p2_3 an2_3 a3,[a3/d3] 70 68 p2_2 an2_2 a2,[a2/d2] 71 69 p2_1 an2_1 a1,[a1/d1] 72 70 p2_0 an2_0 a0,[a0/d0]
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 18 of 85 table 1.14 100-pin package list of pin names (3/3) pin no. control pin port interrupt pin timer pin uart/can pin intelligent i/o pin analog pin bus control pin fp gp 73 71 p1_7 int5 d15 74 72 p1_6 int4 d14 75 73 p1_5 int3 d13 76 74 p1_4 d12 77 75 p1_3 d11 78 76 p1_2 d10 79 77 p1_1 d9 80 78 p1_0 d8 81 79 p0_7 an0_7 d7 82 80 p0_6 an0_6 d6 83 81 p0_5 an0_5 d5 84 82 p0_4 an0_4 d4 85 83 p0_3 an0_3 d3 86 84 p0_2 an0_2 d2 87 85 p0_1 an0_1 d1 88 86 p0_0 an0_0 d0 89 87 p10_7 ki3 rtp3_3 an_7 90 88 p10_6 ki2 rtp3_2 an_6 91 89 p10_5 ki1 rtp3_1 an_5 92 90 p10_4 ki0 rtp3_0 an_4 93 91 p10_3 rtp1_3 an_3 94 92 p10_2 rtp1_2 an_2 95 93 p10_1 rtp1_1 an_1 96 94 avss 97 95 p10_0 rtp1_0 an_0 98 96 vref 99 97 avcc 100 98 p9_7 rxd4/scl4/stxd4 adtrg
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 19 of 85 1.5 pin functions table 1.15 pin functions (100-pin and 144-pin packages) (1/4) i: input o: output i/o: input and output type symbol i/o type supply voltage description power supply vcc1,vcc2 vss ?? apply 3.0 to 5.5 v to pins vcc1 and vcc2, and 0 v to the vss pin. the input condition of vcc1 vcc2 must be met. analog power supply input avcc avss ? vcc1 power supply input pins to th e a/d converter and d/a converter. connect the avcc pin to vcc1, and the avss pin to vss. reset input reset i vcc1 the mcu is placed in the reset state while applying an ?l? signal to the reset pin. cnvss cnvss i vcc1 this pin switches processor mode. apply an ?l? to the cnvss pin to start up in single-chip mode, or an ?h? to start up in microprocessor mode (mask rom, flash memory version) and boot mode (flash memory version). external data bus width select input byte i vcc1 this pin switches a data bus wid th in external memory space 3. a data bus is 16 bits wide when the byte pin is held ?l? and 8 bits wide when it is held ?h?. fix to either ?l? or ?h?. apply an ?l? to the byte pin in single-chip mode. bus control pins d0 to d7 i/o vcc2 data (d0 to d7) input/output pins while accessing an external memory space with separate bus. d8 to d15 i/o vcc2 data (d8 to d15) input/output pins while accessing an external memory space with 16-bit separate bus. a0 to a22 o vcc2 address bits (a0 to a22) output pins. a23 o vcc2 inverted address bit (a23) output pin. a0/d0 to a7/d7 i/o vcc2 data (d0 to d7) input/output and 8 low-order address bits (a0 to a7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. a8/d8 to a15/d15 i/o vcc2 data (d8 to d15) input/output and 8 middle-order address bits (a8 to a15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. cs0 to cs3 o vcc2 chip-select signal output pins used to specify external devices. wrl /wr wrh /bhe rd o vcc2 wrl , wrh , (wr , bhe ) and rd signal output pins. wrl and wrh can be switched with wr and bhe by a program. ?wr l, wrh and rd are selected: if external data bus is 16 bits wide, data is written to an even address in external memory space while an ?l? is output from the wrl pin. data is written to an odd address while an ?l? is output from the wrh pin. data is read while an ?l? is output from the rd pin. ?wr , bhe and rd are selected: data is written while an ?l? is output from the wr pin. data is read while an ?l? is output from the rd pin. data in odd address is accessed while an ?l? is output from the bhe pin. select wr , bhe and rd when an external data bus is 8 bits wide. ale o vcc2 ale signal is used for the external devices to latch address signals when the multiplexe d bus is selected. hold i vcc2 the mcu is placed in a hold state while an ?l? signal is applied to the hold pin. hlda o vcc2 the hlda pin outputs an ?l? while the mcu is placed in a hold state. rdy i vcc2 bus is placed in a wait state while an ?l? signal is applied to the rdy pin.
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 20 of 85 table 1.16 pin functions (100-pin and 144-pin packages) (2/4) i: input o: output i/o: input and output note: 1. the can pins cannot be used in m32c/87b . only can0 pins can be used in m32c/87a . type symbol i/o type supply voltage description main clock input xin i vcc1 input/output pins for the main clock oscillation circuit. connect a ceramic resonator or crystal osc illator between xin and xout. to apply an external clock, apply it to xin and leave xout open. main clock output xout o vcc1 sub clock input xcin i vcc1 input/output pins for the sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout. to apply an external clock, apply it to xcin and leave xcout open. sub clock output xcout o vcc1 bclk output bclk o vcc2 bus clock output pin. clock output clkout o vcc2 the clkout pin outputs the cloc k having the same frequency as fc, f8, or f32. int interrupt input int0 to int2 i vcc1 int interrupt input pins. int3 to int5 i vcc2 nmi interrupt input nmi i vcc1 nmi interrupt input pin. connect the nmi pin to vcc1 via a resistor when the nmi interrupt is not used. timer a ta0out to ta4out i/o vcc1 timer a0 to a4 input/output pins. (ta0out is n-channel open drain output.) ta0in to ta4in i vcc1 timer a0 to a4 input pins. timer b tb0in to tb5in i vcc1 timer b0 to b5 input pins. three-phase motor control timer output u, u , v, v , w, w o vcc1 three-phase motor control timer output pins. serial interface cts0 to cts 5 i vcc1 input pins to control data transmission. rts0 to rts 5 o vcc1 output pins to control data reception. clk0 to clk5 i/o vcc1 serial clock input/output pins. rxd0 to rxd5 i vcc1 serial data input pins. txd0 to txd5 o vcc1 serial data output pins. (txd2 is n-channel open drain output.) i 2 c mode sda0 to sda4 i/o vcc1 serial data input/output pins. (sda2 is n-channel open drain output.) scl0 to scl4 i/o vcc1 serial clock input/output pins. (scl2 is n-channel open drain output.) serial interface special function stxd0 to stxd4 o vcc1 serial data output pins when slave mode is selected. (stxd2 is n-channel open drain output.) srxd0 to srxd4 i vcc1 serial data input pins when slave mode is selected. ss0 to ss4 i vcc1 control input pins used in the serial interface special mode. irda irdain i vcc1 irda serial data input pin. irdaout o vcc1 irda serial data output pin. can (1) can0in, can1in i vcc1 received data input pins for the can communication function. can0out, can1out o vcc1 transmit data output pins for the can communication function. can1wu i vcc1 can wake-up interrupt input pin.
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 21 of 85 table 1.17 pin functions (100-pin and 144-pin package) (3/4) i: input o: output i/o: input and output note: 1. only vcc1 can be used in the 100-pin package. type symbol i/o type supply voltage description intelligent i/o inpc1_0 to inpc1_3 ivcc1/ vcc2 (1) input pins for the time measurement function. inpc1_4 to inpc1_7 i vcc1 outc1_0 to outc1_3 ovcc1/ vcc2 (1) output pins for the waveform generation function. (outc1_6/outc2_0 and outc1_7/outc2_2 assigned to ports 7_0 and 7_1 are n-channel open drain output.) outc1_4 to outc1_7 o vcc1 outc2_0 to outc2_2 ovcc1/ vcc2 (1) isclk0 i/o vcc1 clock input/output pins fo r the intelligent i/o communication function. isclk1, isclk2 i/o vcc1/ vcc2 (1) isrxd0 i vcc1 data input pins for the intelligent i/o communication function. isrxd1, isrxd2 ivcc1/ vcc2 (1) istxd0 o vcc1 data output pins for the intelligent i/o communication function. (istxd2 assigned to port 7_0 is n-channel open drain output.) istxd1, istxd2 ovcc1/ vcc2 (1) iein i vcc1/ vcc2 (1) data input pin for the intelligent i/o communication function. ieout o vcc1/ vcc2 (1) data output pin for the intelligent i/o communication function. (ieout assigned to port 7_0 is n-channel open drain output.) reference voltage input vref i ? the vref pin supplies the referenc e voltage to the a/d converter and d/a converter. a/d converter an_0 to an_7 i vcc1 analog input pins for the a/d converter. an0_0 to an0_7, an2_0 to an2_7 i vcc2 adtrg i vcc1 external trigger input pin for the a/d converter. anex0 i/o vcc1 extended analog input pin for the a/d converter or output pin in external op-amp connection mode. anex1 i vcc1 extended analog input pin for the a/d converter. d/a converter da0, da1 o vcc1 output pins for the d/a converter. real-time port rtp0_0 to rtp0_3 rtp1_0 to rtp1_3 rtp2_0 to rtp2_3 rtp3_0 to rtp3_3 o vcc1 these pins function as real-time ports. (rtp0_2 and rtp0_3 are n-channel open drain output.)
m32c/87 group (m32c/87, m32c /87a, m32c/87b) 1. overview rej03b0127-0151 rev.1.51 jul 31, 2008 page 22 of 85 table 1.18 pin functions (100-pin and 144-pin package) (4/4) i: input o: output i/o: input and output table 1.19 pin functions (144-pin package only) i: input o: output i/o: input and output type symbol i/o type supply voltage description i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 i/o vcc2 8-bit cmos i/o ports. the port pi direction register (i = 0 to 15) determines if each pin is used as an input port or an output port. the pull-up control registers determine if the input ports, divided into groups of four, are pulled up or not. p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7 i/o vcc1 these 8-bit i/o ports are functionally equivalent to p0. (p7_0 and p7_1 are n-channel open drain output.) p8_0 to p8_4 p8_6, p8_7 i/o vcc1 these i/o ports are functionally equivalent to p0. input port p8_5 i vcc1 shares the pin with nmi . input port to read nmi pin level. key input interrupt input ki0 to ki3 i vcc1 key input interrupt input pins. type symbol i/o type supply voltage description int interrupt input int6 to int8 i vcc1 int interrupt input pins. serial interface cts6 ivcc1/ vcc2 input pin to control data transmission. rts6 ovcc1/ vcc2 output pin to control data reception. clk6 i/o vcc1/ vcc2 serial clock input/output pin. rxd6 i vcc1/ vcc2 serial data input pin. txd6 o vcc1/ vcc2 serial data output pin. intelligent i/o outc2_3 to outc2_7 o vcc2 output pins for the waveform generation function. a/d converter an15_0 to an15_7 i vcc1 analog input pins for the a/d converter. i/o port p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 i/o vcc2 these i/o ports are functionally equivalent to p0. p14_0 to p14_6, p15_0 to p15_7 i/o vcc1 these i/o ports are functionally equivalent to p0.
m32c/87 group (m32c/87, m32c/87a, m32c/ 87b) 2. central processing unit (cpu) rej03b0127-0151 rev.1.51 jul 31, 2008 page 23 of 85 2. central processi ng unit (cpu) r0h r0l r1h r1l r2 r3 r2 r3 a0 a1 sb fb static base register (1) frame base register (1) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved processor interrupt priority level reserved r0l r1l r2 r3 r2 r3 a0 a1 sb fb usp intb isp pc r0h r1h b31 b15 b23 b0 flg c d z s b o i u ipl b15 b0 b8 b7 svf svp vct b23 b15 b0 dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dra0 dra1 dsa0 dsa1 b23 b15 b0 b7 address registers (1) user stack pointer interrupt stack pointer interrupt table register program counter flag register general registers high-speed interrupt registers dmac-associated registers flag save register pc save register vector register dma mode registers dma transfer count registers dma transfer count reload registers dma memory address registers dma memory address reload registers dma sfr address registers note: 1. these registers comprise a register bank. there are two sets of register banks (register bank 0 and register bank 1). data registers (1) figure 2.1 shows the cpu registers. the register bank is comprised of eight registers (r0, r1, r2, r3, a0, a1, sb, and fb) out of 28 cpu registers. there are two sets of register banks. figure 2.1 cpu register
m32c/87 group (m32c/87, m32c/87a, m32c/ 87b) 2. central processing unit (cpu) rej03b0127-0151 rev.1.51 jul 31, 2008 page 24 of 85 2.1 general registers 2.1.1 data registers (r0, r1, r2, and r3) r0, r1, r2, and r3 are 16-bit registers for transfer, arith metic and logic operations. r0 and r1 can be split into high-order (r0h/r1h) and low-order bits (r0l/r1l) to be used separately as 8-bit data registers. r0 can be combined with r2 and used as a 32-bit data register (r2r0). the same applies to r3r1. 2.1.2 address registers (a0 and a1) a0 and a1 are 24-bit registers used for a0-/a1-indir ect addressing, a0-/a1-relative addressing, transfer, arithmetic and logic operations. 2.1.3 static base register (sb) sb is a 24-bit register used for sb-relative addressing. 2.1.4 frame base register (fb) fb is a 24-bit register used for fb-relative addressing. 2.1.5 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointers (sp), usp and isp, ar e 24 bits wide each. the u flag is us ed to switch between usp and isp. refer to 2.1.8 flag register (flg) for details on the u flag. set usp and isp to even addresses to execute an interrupt sequence efficiently. 2.1.6 interrupt table register (intb) intb is a 24-bit register indicating the starting address of a relocatable interrupt vector table. 2.1.7 program counter (pc) pc is 24 bits wide and indicates the address of the next instruction to be executed. 2.1.8 flag register (flg) flg is a 16-bit register indicating the cpu state. 2.1.8.1 carry flag (c) the c flag indicates whether or no t carry or borrow has been generated after executing an instruction. 2.1.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.1.8.3 zero flag (z) the z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0. 2.1.8.4 sign flag (s) the s flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0. 2.1.8.5 register bank select flag (b) register bank 0 is selected when the b flag is set to 0. register bank 1 is selected when this flag is set to 1. 2.1.8.6 overflow flag (o) the o flag becomes 1 when an arithmetic operat ion results in an overflow; otherwise becomes 0.
m32c/87 group (m32c/87, m32c/87a, m32c/ 87b) 2. central processing unit (cpu) rej03b0127-0151 rev.1.51 jul 31, 2008 page 25 of 85 2.1.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0 and enabled when it is set to 1. the i flag becomes 0 when an interrupt request is acknowledged. 2.1.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0. usp is selected when the u flag is set to 1. the u flag becomes 0 when a hardware interrupt reque st is acknowledged or the int instruction specifying software interrupt numbers 0 to 31 is executed. 2.1.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priority level than ipl, the interrupt is enabled. 2.1.8.10 reserved space only write 0 to bits assigned to the reserved space. when read, the bits return undefined values. 2.2 high-speed interrupt registers registers associated w ith the high-speed interrupt are as follows: ? flag save register (svf) ? pc save register (svp) ? vector register (vct) 2.3 dmac-associated registers registers associated with the dmac are as follows: ? dma mode register (dmd0, dmd1) ? dma transfer count register (dct0, dct1) ? dma transfer count reload register (drc0, drc1) ? dma memory address register (dma0, dma1) ? dma memory address reload register (dra0, dra1) ? dma sfr address register (dsa0, dsa1)
m32c/87 group (m32c/87, m32c/87a, m32c/87b) 3. memory rej03b0127-0151 rev.1.51 jul 31, 2008 page 26 of 85 3. memory figure 3.1 shows a memory map of the m32c/87 group (m32c/87, m32c/87a, m32c/87b). the m32c/87 group (m32c/87, m32c/87a, m32c/87b) has 16-mbyte address space from addresses 000000h to ffffffh. the internal rom is allocated in lower addresses, beginning with a ddress ffffffh. for example, a 512-kbyte internal rom area is allocated in addresses f80000h to ffffffh. the fixed interrupt vectors are allocated in addresses ffff dch to ffffffh. they store th e starting address of each interrupt routine. the internal ram is allocated higher addresses, beginning with address 000400h. for example, a 48-kbyte internal ram area is allocated in addresses 000400h to 00c3ffh. the internal ram is used not only for storing data but for the stacks when subroutines are called or when interrupt requests are acknowledged. sfrs are allocated in addresses 000000h to 0003ffh. the periph eral function control registers such as for i/o ports, a/d converters, serial interfaces, timers are allocated here. all blank spaces w ithin sfrs are reserved and cannot be accessed by users. the special page vectors are allocated addresses fffe00h to ffffdbh. they are used for the jmps instruction and jsrs instruction. refer to the renesas publication m32c/80 series software manual for details. figure 3.1 memory map notes: 1. the space is used as the exte rnal space in memory expansion mode and in microprocessor mode. it is reserved in single-ship mode. 2. the space is reserved in me mory expansion mode. it is used as the external space in microprocessor mode. 3. additional 4-kbyte space is provided in the flash me mory version to store data. th is space is used in single-chip mode and memory expansion mode. it is reserved in microprocessor mode. 4. this space is used in single-chip mode and me mory expansion mode. it is us ed as the external space in microprocessor mode. 5. the watchdog timer interrupt, oscillation stop detection interrupt, and vdet4 detection inte rrupt use the same vector. 000000h 000400h xxxxxxh 00f000h f00000h yyyyyyh ffffffh ffffffh ffffdch fffe00h 00ffffh capacity xxxxxxh 0063ffh internal ram 24 kbytes reset watchdog timer (5) address match brk instruction overflow undefined instruction special page vector table sfr internal ram reserved external space (1) reserved (2) internal rom (4) internal rom (3) (data space) nmi capacity yyyyyyh fa0000h internal rom 384 kbytes 007fffh 31 kbytes 00c3ffh 48 kbytes f80000h 512 kbytes f40000h 768 kbytes f00000h 1024 kbytes
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 27 of 85 4. special function registers (sfrs) special function registers (sfrs) are the control registers of peripheral functions. tables 4.1 to 4.20 list sfr address maps. table 4.1 sfr address map (1/20) x: undefined blank spaces are all reserved. no access is allowed. note: 1. bits pm01 and pm00 in the pm0 register maintain values set before reset, even after software reset or watchdog timer reset ha s been performed. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 (1) pm0 1000 0000b(cnvss=?l?) 0000 0011b(cnvss=?h?) 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 0000 1000b 0007h system clock control register 1 cm1 0010 0000b 0008h 0009h address match interrupt enable register aier 00h 000ah protect register prcr xxxx 0000b 000bh external data bus width control register ds xxxx 1000b(byte=?l?) xxxx 0000b(byte=?h?) 000ch main clock division register mcd xxx0 1000b 000dh oscillation stop detection register cm2 00h 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00xx xxxxb 0010h address match interrupt register 0 rmad0 000000h 0011h 0012h 0013h processor mode register 2 pm2 00h 0014h address match interrupt register 1 rmad1 000000h 0015h 0016h 0017h voltage detection register 2 vcr2 00h 0018h address match interrupt register 2 rmad2 000000h 0019h 001ah 001bh voltage detection register 1 vcr1 0000 1000b 001ch address match interrupt register 3 rmad3 000000h 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h pll control register 0 plc0 0001 x010b 0027h pll control register 1 plc1 000x 0000b 0028h address match interrupt register 4 rmad4 000000h 0029h 002ah 002bh 002ch address match interrupt register 5 rmad5 000000h 002dh 002eh 002fh vdet4 detection interrupt register d4int xx00 0000b
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 28 of 85 table 4.2 sfr address map (2/20) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h address match interrupt register 6 rmad6 000000h 0039h 003ah 003bh 003ch address match interrupt register 7 rmad7 000000h 003dh 003eh 003fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h external space wait control register 0 ewcr0 x0x0 0011b 0049h external space wait control register 1 ewcr1 x0x0 0011b 004ah external space wait control register 2 ewcr2 x0x0 0011b 004bh external space wait control register 3 ewcr3 x0x0 0011b 004ch 004dh 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h flash memory control register 1 fmr1 0000 0x0xb 0056h 0057h flash memory control register 0 fmr0 0000 0001b(flash memory) xxxx xxx0b(mask rom) 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 29 of 85 table 4.3 sfr address map (3/20) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h dma0 interrupt control register dm0ic xxxx x000b 0069h timer b5 interrupt control register tb5ic xxxx x000b 006ah dma2 interrupt control register dm2ic xxxx x000b 006bh uart2 receive/ack interrupt control register s2ric xxxx x000b 006ch timer a0 interrupt control register ta0ic xxxx x000b 006dh uart3 receive/ack interrupt control register s3ric xxxx x000b 006eh timer a2 interrupt control register ta2ic xxxx x000b 006fh uart4 receive/ack interrupt control register s4ric xxxx x000b 0070h timer a4 interrupt control register ta4ic xxxx x000b 0071h uart0/uart3 bus conflict detection interrupt control register bcn0ic/bcn3ic xxxx x000b 0072h uart0 receive/ack interrupt control register s0ric xxxx x000b 0073h a/d0 conversion interrupt control register ad0ic xxxx x000b 0074h uart1 receive/ack interrupt control register s1ric xxxx x000b 0075h ii/o interrupt control register 0 / can1 interrupt control register 0 iio0ic/can3ic xxxx x000b 0076h timer b1 interrupt control register tb1ic xxxx x000b 0077h ii/o interrupt control register 2 iio2ic xxxx x000b 0078h timer b3 interrupt control register tb3ic xxxx x000b 0079h ii/o interrupt control register 4 iio4ic xxxx x000b 007ah int5 interrupt control register int5ic xx00 x000b 007bh ii/o interrupt control register 6 iio6ic xxxx x000b 007ch int3 interrupt control register int3ic xx00 x000b 007dh ii/o interrupt control register 8 iio8ic xxxx x000b 007eh int1 interrupt control register int1ic xx00 x000b 007fh ii/o interrupt control register 10 / can0 interrupt control register 1 iio10ic/can1ic xxxx x000b 0080h 0081h ii/o interrupt control register 11 / can0 interrupt control register 2 iio11ic/can2ic xxxx x000b 0082h 0083h 0084h 0085h 0086h 0087h 0088h dma1 interrupt control register dm1ic xxxx x000b 0089h uart2 transmit/nack interrupt control register s2tic xxxx x000b 008ah dma3 interrupt control register dm3ic xxxx x000b 008bh uart3 transmit/nack interrupt control register s3tic xxxx x000b 008ch timer a1 interrupt control register ta1ic xxxx x000b 008dh uart4 transmit/nack interrupt control register s4tic xxxx x000b 008eh timer a3 interrupt control register ta3ic xxxx x000b 008fh uart2 bus conflict detection interrupt control register bcn2ic xxxx x000b
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 30 of 85 table 4.4 sfr address map (4/20) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0090h uart0 transmit/nack interrupt control register s0tic xxxx x000b 0091h uart1/uart4 bus conflict detection interrupt control register bcn1ic/bcn4ic xxxx x000b 0092h uart1 transmit/nack interrupt control register s1tic xxxx x000b 0093h key input interrupt control register kupic xxxx x000b 0094h timer b0 interrupt control register tb0ic xxxx x000b 0095h ii/o interrupt control register 1 / can1 interrupt control register 1 iio1ic/can4ic xxxx x000b 0096h timer b2 interrupt control register tb2ic xxxx x000b 0097h ii/o interrupt control register 3 iio3ic xxxx x000b 0098h timer b4 interrupt control register tb4ic xxxx x000b 0099h ii/o interrupt control register 5 /can1 interrupt control register 2 iio5ic/can5ic xxxx x000b 009ah int4 interrupt control register int4ic xx00 x000b 009bh ii/o interrupt control register 7 iio7ic xxxx x000b 009ch int2 interrupt control register int2ic xx00 x000b 009dh ii/o interrupt control register 9 / can0 inte rrupt control register 0 iio9ic/can0ic xxxx x000b 009eh int0 interrupt control register int0ic xx00 x000b 009fh exit priority register rlvl xxxx 0000b 00a0h interrupt request register 0 iio0ir 0000 000xb 00a1h interrupt request register 1 iio1ir 0000 000xb 00a2h interrupt request register 2 iio2ir 0000 000xb 00a3h interrupt request register 3 iio3ir 0000 000xb 00a4h interrupt request register 4 iio4ir 0000 000xb 00a5h interrupt request register 5 iio5ir 0000 000xb 00a6h interrupt request register 6 iio6ir 0000 000xb 00a7h interrupt request register 7 iio7ir 0000 000xb 00a8h interrupt request register 8 iio8ir 0000 000xb 00a9h interrupt request register 9 iio9ir 0000 000xb 00aah interrupt request register 10 iio10ir 0000 000xb 00abh interrupt request register 11 iio11ir 0000 000xb 00ach 00adh 00aeh 00afh 00b0h interrupt enable register 0 iio0ie 00h 00b1h interrupt enable register 1 iio1ie 00h 00b2h interrupt enable register 2 iio2ie 00h 00b3h interrupt enable register 3 iio3ie 00h 00b4h interrupt enable register 4 iio4ie 00h 00b5h interrupt enable register 5 iio5ie 00h 00b6h interrupt enable register 6 iio6ie 00h 00b7h interrupt enable register 7 iio7ie 00h 00b8h interrupt enable register 8 iio8ie 00h 00b9h interrupt enable register 9 iio9ie 00h 00bah interrupt enable register 10 iio10ie 00h 00bbh interrupt enable register 11 iio11ie 00h 00bch 00bdh 00beh 00bfh to 00dfh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 31 of 85 table 4.5 sfr address map (5/20) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 00e0h 00e1h 00e2h 00e3h 00e4h 00e5h 00e6h 00e7h 00e8h group 0 si/o receive buffer register g0rb xxxx xxxxb 00e9h xxx0 xxxxb 00eah group 0 transmit buffer/receive data register g0tb/g0dr xxh 00ebh 00ech group 0 receive input register g0ri xxh 00edh group 0 si/o communication mode register g0mr 00h 00eeh group 0 transmit output register g0to xxh 00efh group 0 si/o communication control register g0cr 0000 x011b 00f0h group 0 data compare register 0 g0cmp0 xxh 00f1h group 0 data compare register 1 g0cmp1 xxh 00f2h group 0 data compare register 2 g0cmp2 xxh 00f3h group 0 data compare register 3 g0cmp3 xxh 00f4h group 0 data mask register 0 g0msk0 xxh 00f5h group 0 data mask register 1 g0msk1 xxh 00f6h communication clock select register ccs xxxx 0000b 00f7h 00f8h group 0 receive crc code register g0rcrc xxxxh 00f9h 00fah group 0 transmit crc code register g0tcrc 0000h 00fbh 00fch group 0 si/o expansion mode register g0emr 00h 00fdh group 0 si/o extended receive control register g0erc 00h 00feh group 0 si/o special communication interrupt detection register g0irf 0000 xxxxb 00ffh group 0 si/o extended transmit control register g0etc 0000 0xxxb 0100h group 1 time measurement/waveform generation register 0 g1tm0/g1po0 xxxxh 0101h 0102h group 1 time measurement/waveform generation register 1 g1tm1/g1po1 xxxxh 0103h 0104h group 1 time measurement/waveform generation register 2 g1tm2/g1po2 xxxxh 0105h 0106h group 1 time measurement/waveform generation register 3 g1tm3/g1po3 xxxxh 0107h 0108h group 1 time measurement/waveform generation register 4 g1tm4/g1po4 xxxxh 0109h 010ah group 1 time measurement/waveform generation register 5 g1tm5/g1po5 xxxxh 010bh 010ch group 1 time measurement/waveform generation register 6 g1tm6/g1po6 xxxxh 010dh 010eh group 1 time measurement/waveform generation register 7 g1tm7/g1po7 xxxxh 010fh 0110h group 1 waveform generation control register 0 g1pocr0 0000 x000b 0111h group 1 waveform generation control register 1 g1pocr1 0x00 x000b 0112h group 1 waveform generation control register 2 g1pocr2 0x00 x000b 0113h group 1 waveform generation control register 3 g1pocr3 0x00 x000b 0114h group 1 waveform generation control register 4 g1pocr4 0x00 x000b 0115h group 1 waveform generation control register 5 g1pocr5 0x00 x000b 0116h group 1 waveform generation control register 6 g1pocr6 0x00 x000b 0117h group 1 waveform generation control register 7 g1pocr7 0x00 x000b 0118h group 1 time measurement control register 0 g1tmcr0 00h 0119h group 1 time measurement control register 1 g1tmcr1 00h
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 32 of 85 table 4.6 sfr address map (6/20) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 011ah group 1 time measurement control register 2 g1tmcr2 00h 011bh group 1 time measurement control register 3 g1tmcr3 00h 011ch group 1 time measurement control register 4 g1tmcr4 00h 011dh group 1 time measurement control register 5 g1tmcr5 00h 011eh group 1 time measurement control register 6 g1tmcr6 00h 011fh group 1 time measurement control register 7 g1tmcr7 00h 0120h group 1 base timer register g1bt xxxxh 0121h 0122h group 1 base timer control register 0 g1bcr0 00h 0123h group 1 base timer control register 1 g1bcr1 x000 000xb 0124h group 1 time measurement prescaler register 6 g1tpr6 00h 0125h group 1 time measurement prescaler register 7 g1tpr7 00h 0126h group 1 function enable register g1fe 00h 0127h group 1 function select register g1fs 00h 0128h group 1 si/o receive buffer register g1rb xxxx xxxxb 0129h x000 xxxxb 012ah group 1 transmit buffer/receive data register g1tb/g1dr xxh 012bh 012ch group 1 receive input register g1ri xxh 012dh group 1 si/o communication mode register g1mr 00h 012eh group 1 transmit output register g1to xxh 012fh group 1 si/o communication control register g1cr 0000 x011b 0130h group 1 data compare register 0 g1cmp0 xxh 0131h group 1 data compare register 1 g1cmp1 xxh 0132h group 1 data compare register 2 g1cmp2 xxh 0133h group 1 data compare register 3 g1cmp3 xxh 0134h group 1 data mask register 0 g1msk0 xxh 0135h group 1 data mask register 1 g1msk1 xxh 0136h 0137h 0138h group 1 receive crc code register g1rcrc xxxxh 0139h 013ah group 1 transmit crc code register g1tcrc 0000h 013bh 013ch group 1 si/o expansion mode register g1emr 00h 013dh group 1 si/o extended receive control register g1erc 00h 013eh group 1 si/o special communication interrupt detection register g1irf 0000 xxxxb 013fh group 1 si/o extended transmit control register g1etc 0000 0xxxb 0140h group 2 waveform generation register 0 g2po0 xxxxh 0141h 0142h group 2 waveform generation register 1 g2po1 xxxxh 0143h 0144h group 2 waveform generation register 2 g2po2 xxxxh 0145h 0146h group 2 waveform generation register 3 g2po3 xxxxh 0147h 0148h group 2 waveform generation register 4 g2po4 xxxxh 0149h 014ah group 2 waveform generation register 5 g2po5 xxxxh 014bh 014ch group 2 waveform generation register 6 g2po6 xxxxh 014dh 014eh group 2 waveform generation register 7 g2po7 xxxxh 014fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 33 of 85 table 4.7 sfr address map (7/20) x: undefined blank spaces are all rese rved. no access is allowed. address register symbol after reset 0150h group 2 waveform generation control register 0 g2pocr0 00h 0151h group 2 waveform generation control register 1 g2pocr1 00h 0152h group 2 waveform generation control register 2 g2pocr2 00h 0153h group 2 waveform generation control register 3 g2pocr3 00h 0154h group 2 waveform generation control register 4 g2pocr4 00h 0155h group 2 waveform generation control register 5 g2pocr5 00h 0156h group 2 waveform generation control register 6 g2pocr6 00h 0157h group 2 waveform generation control register 7 g2pocr7 00h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h group 2 base timer register g2bt xxxxh 0161h 0162h group 2 base timer control register 0 g2bcr0 00h 0163h group 2 base timer control register 1 g2bcr1 00h 0164h base timer start register btsr xxxx 0000b 0165h 0166h group 2 function enable register g2fe 00h 0167h group 2 rtp output buffer register g2rtp 00h 0168h 0169h 016ah group 2 si/o communication mode register g2mr 00xx x000b 016bh group 2 si/o communication control register g2cr 0000 x000b 016ch group 2 si/o transmit buffer register g2tb xxxxh 016dh 016eh group 2 si/o receive buffer register g2rb xxxxh 016fh 0170h group 2 iebus address register iear xxxxh 0171h 0172h group 2 iebus control register iecr 00xx x000b 0173h group 2 iebus transmit interrupt source detection register ietif xxx0 0000b 0174h group 2 iebus receive interrupt source detection register ierif xxx0 0000b 0175h 0176h 0177h input function select register b ipsb 00h 0178h input function select register ips 00h 0179h input function select register a ipsa 00h 017ah 017bh 017ch 017dh to 01bfh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 34 of 85 table 4.8 sfr address map (8/20) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. the can-associated registers (allocated in addresses 01e0h to 02 bfh) cannot be used in m32c/87b. in m32c/87a, only can0-assoc iated registers can be used. 2. set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers. address register symbol after reset 01c0h uart5 transmit/receive mode register u5mr 00h 01c1h uart5 baud rate register u5brg xxh 01c2h uart5 transmit buffer register u5tb xxxxh 01c3h 01c4h uart5 transmit/receive control register 0 u5c0 0000 1000b 01c5h uart5 transmit/receive control register 1 u5c1 xxxx 0010b 01c6h uart5 receive buffer register u5rb xxxxh 01c7h 01c8h uart6 transmit/receive mode register u6mr 00h 01c9h uart6 baud rate register u6brg xxh 01cah uart6 transmit buffer register u6tb xxxxh 01cbh 01cch uart6 transmit/receive control register 0 u6c0 0000 1000b 01cdh uart6 transmit/receive control register 1 u6c1 xxxx 0010b 01ceh uart6 receive buffer register u6rb xxxxh 01cfh 01d0h uart5, uart6 transmit/receive control register u56con x000 0000b 01d1h uart5, uart6 input pin function select register u56is x000 x000b 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h rtp output buffer register 0 rtp0r xxh 01d9h rtp output buffer register 1 rtp1r xxh 01dah rtp output buffer register 2 rtp2r xxh 01dbh rtp output buffer register 3 rtp3r xxh 01dch 01ddh 01deh 01dfh 01e0h can0 message slot buffer 0 standard id0 (1)(2) c0slot0_0 xxh 01e1h can0 message slot buffer 0 standard id1 (1)(2) c0slot0_1 xxh 01e2h can0 message slot buffer 0 extended id0 (1)(2) c0slot0_2 xxh 01e3h can0 message slot buffer 0 extended id1 (1)(2) c0slot0_3 xxh 01e4h can0 message slot buffer 0 extended id2 (1)(2) c0slot0_4 xxh 01e5h can0 message slot buffer 0 data length code (1)(2) c0slot0_5 xxh 01e6h can0 message slot buffer 0 data 0 (1)(2) c0slot0_6 xxh 01e7h can0 message slot buffer 0 data 1 (1)(2) c0slot0_7 xxh 01e8h can0 message slot buffer 0 data 2 (1)(2) c0slot0_8 xxh 01e9h can0 message slot buffer 0 data 3 (1)(2) c0slot0_9 xxh 01eah can0 message slot buffer 0 data 4 (1)(2) c0slot0_10 xxh 01ebh can0 message slot buffer 0 data 5 (1)(2) c0slot0_11 xxh 01ech can0 message slot buffer 0 data 6 (1)(2) c0slot0_12 xxh 01edh can0 message slot buffer 0 data 7 (1)(2) c0slot0_13 xxh 01eeh can0 message slot buffer 0 time stamp high-order (1)(2) c0slot0_14 xxh 01efh can0 message slot buffer 0 time stamp low-order (1)(2) c0slot0_15 xxh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 35 of 85 table 4.9 sfr address map (9/20) x: undefined blank spaces are all rese rved. no access is allowed. notes: 1. values are obtained by setting the sleep bit in the c0slpr register to ?1? (sleep mode exited) after reset and supplying a cl ock to the can module. 2. the can-associated registers (allocated in addresses 01e0h to 02 bfh) cannot be used in m32c/87b. in m32c/87a, only can0-assoc iated registers can be used. 3. set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers. address register (2)(3) symbol after reset 01f0h can0 message slot buffer 1 standard id0 c0slot1_0 xxh 01f1h can0 message slot buffer 1 standard id1 c0slot1_1 xxh 01f2h can0 message slot buffer 1 extended id0 c0slot1_2 xxh 01f3h can0 message slot buffer 1 extended id1 c0slot1_3 xxh 01f4h can0 message slot buffer 1 extended id2 c0slot1_4 xxh 01f5h can0 message slot buffer 1 data length code c0slot1_5 xxh 01f6h can0 message slot buffer 1 data 0 c0slot1_6 xxh 01f7h can0 message slot buffer 1 data 1 c0slot1_7 xxh 01f8h can0 message slot buffer 1 data 2 c0slot1_8 xxh 01f9h can0 message slot buffer 1 data 3 c0slot1_9 xxh 01fah can0 message slot buffer 1 data 4 c0slot1_10 xxh 01fbh can0 message slot buffer 1 data 5 c0slot1_11 xxh 01fch can0 message slot buffer 1 data 6 c0slot1_12 xxh 01fdh can0 message slot buffer 1 data 7 c0slot1_13 xxh 01feh can0 message slot buffer 1 time stamp high-order c0slot1_14 xxh 01ffh can0 message slot buffer 1 time stamp low-order c0slot1_15 xxh 0200h can0 control register 0 c0ctlr0 xx01 0x01b (1) 0201h xxxx 0000b (1) 0202h can0 status register c0str 0000 0000b (1) 0203h x000 0x01b (1) 0204h can0 extended id register c0idr 0000h (1) 0205h 0206h can0 configuration register c0conr 0000 xxxxb (1) 0207h 0000 0000b (1) 0208h can0 time stamp register c0tsr 0000h (1) 0209h 020ah can0 transmit error count register c0tec 00h (1) 020bh can0 receive error count register c0rec 00h (1) 020ch can0 slot interrupt status register c0sistr 0000h (1) 020dh 020eh 020fh 0210h can0 slot interrupt mask register c0simkr 0000h (1) 0211h 0212h 0213h 0214h can0 error interrupt mask register c0eimkr xxxx x000b (1) 0215h can0 error interrupt status register c0eistr xxxx x000b (1) 0216h can0 error source register c0efr 00h (1) 0217h can0 baud rate prescaler c0brp 0000 0001b (1) 0218h 0219h can0 mode register c0mdr xxxx xx00b (1) 021ah 021bh 021ch 021dh 021eh 021fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 36 of 85 table 4.10 sfr address map (10/20) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. the banksel bit in the c0ctlr1 register ca n switch functions for addresses 0220h to 023fh. 2. values are obtained by setting the sleep bit in the c0slpr register to ?1? (sleep mode exited) after reset and supplying a cl ock to the can module. 3. the can-associated registers (allocated in addresses 01e0h to 02 bfh) cannot be used in m32c/87b. in m32c/87a, only can0-assoc iated registers can be used. 4. set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers. address register (3)(4) symbol after reset 0220h can0 single shot control register c0ssctlr 0000h (1)(2) 0221h 0222h 0223h 0224h can0 single shot status register c0ssstr 0000h (1)(2) 0225h 0226h 0227h 0228h can0 global mask register standard id0 c0gmr0 xxx0 0000b (1)(2) 0229h can0 global mask register standard id1 c0gmr1 xx00 0000b (1)(2) 022ah can0 global mask register extended id0 c0gmr2 xxxx 0000b (1)(2) 022bh can0 global mask register extended id1 c0gmr3 00h (1)(2) 022ch can0 global mask register extended id2 c0gmr4 xx00 0000b (1)(2) 022dh 022eh 022fh 0230h can0 message slot 0 control register / can0 local mask register a standard id0 c0mctl0 / c0lmar0 0000 0000b (1)(2) / xxx0 0000b (1)(2) 0231h can0 message slot 1 control register / can0 local mask register a standard id1 c0mctl1 / c0lmar1 0000 0000b (1)(2) / xx00 0000b (1)(2) 0232h can0 message slot 2 control register / can0 local mask register a extended id0 c0mctl2 / c0lmar2 0000 0000b (1)(2) / xxxx 0000b (1)(2) 0233h can0 message slot 3 control register / can0 local mask register a extended id1 c0mctl3 / c0lmar3 00h (1)(2) / 00h (1)(2) 0234h can0 message slot 4 control register / can0 local mask register a extended id2 c0mctl4 / c0lmar4 0000 0000b (1)(2) / xx00 0000b (1)(2) 0235h can0 message slot 5 control register c0mctl5 00h (1)(2) 0236h can0 message slot 6 control register c0mctl6 00h (1)(2) 0237h can0 message slot 7 control register c0mctl7 00h (1)(2) 0238h can0 message slot 8 control register / can0 local mask register b standard id0 c0mctl8 / c0lmbr0 0000 0000b (1)(2) / xxx0 0000b (1)(2) 0239h can0 message slot 9 control register / can0 local mask register b standard id1 c0mctl9 / c0lmbr1 0000 0000b (1)(2) / xx00 0000b (1)(2) 023ah can0 message slot 10 control register / can0 local mask register b extended id0 c0mctl10 / c0lmbr2 0000 0000b (1)(2) / xxxx 0000b (1)(2) 023bh can0 message slot 11 control register / can0 local mask register b extended id1 c0mctl11 / c0lmbr3 00h (1)(2) / 00h (1)(2) 023ch can0 message slot 12 control register / can0 local mask register b extended id2 c0mctl12 / c0lmbr4 0000 0000b (1)(2) / xx00 0000b (1)(2) 023dh can0 message slot 13 control register c0mctl13 00h (1)(2) 023eh can0 message slot 14 control register c0mctl14 00h (1)(2) 023fh can0 message slot 15 control register c0mctl15 00h (1)(2) 0240h can0 slot buffer select register c0sbs 00h (2) 0241h can0 control register 1 c0ctlr1 x000 00xxb (2) 0242h can0 sleep control register c0slpr xxxx xxx0b 0243h 0244h can0 acceptance filter support register c0afs 0000 0000b (2) 0245h 0000 0001b (2) 0246h 0247h 0248h 0249h 024ah to 024fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 37 of 85 table 4.11 sfr address map (11/20) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. values are obtained by setting the sleep bit in the c1slpr register to ?1? (sleep mode exited) after reset and supplying a cl ock to the can module. 2. the can-associated registers (allocated in addresses 01e0h to 02 bfh) cannot be used in m32c/87b. in m32c/87a, only can0-assoc iated registers can be used. 3. set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers. address register (2)(3) symbol after reset 0250h can1 slot buffer select register c1sbs 00h (1) 0251h can1 control register 1 c1ctlr1 x000 00xxb (1) 0252h can1 sleep control register c1slpr xxxx xxx0b (1) 0253h 0254h can1 acceptance filter support register c1afs 0000 0000b (1) 0255h 0000 0001b (1) 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h can1 message slot buffer 0 standard id0 c1slot0_0 xxh 0261h can1 message slot buffer 0 standard id1 c1slot0_1 xxh 0262h can1 message slot buffer 0 extended id0 c1slot0_2 xxh 0263h can1 message slot buffer 0 extended id1 c1slot0_3 xxh 0264h can1 message slot buffer 0 extended id2 c1slot0_4 xxh 0265h can1 message slot buffer 0 data length code c1slot0_5 xxh 0266h can1 message slot buffer 0 data 0 c1slot0_6 xxh 0267h can1 message slot buffer 0 data 1 c1slot0_7 xxh 0268h can1 message slot buffer 0 data 2 c1slot0_8 xxh 0269h can1 message slot buffer 0 data 3 c1slot0_9 xxh 026ah can1 message slot buffer 0 data 4 c1slot0_10 xxh 026bh can1 message slot buffer 0 data 5 c1slot0_11 xxh 026ch can1 message slot buffer 0 data 6 c1slot0_12 xxh 026dh can1 message slot buffer 0 data 7 c1slot0_13 xxh 026eh can1 message slot buffer 0 time stamp high-order c1slot0_14 xxh 026fh can1 message slot buffer 0 time stamp low-order c1slot0_15 xxh 0270h can1 message slot buffer 1 standard id0 c1slot1_0 xxh 0271h can1 message slot buffer 1 standard id1 c1slot1_1 xxh 0272h can1 message slot buffer 1 extended id0 c1slot1_2 xxh 0273h can1 message slot buffer 1 extended id1 c1slot1_3 xxh 0274h can1 message slot buffer 1 extended id2 c1slot1_4 xxh 0275h can1 message slot buffer 1 data length code c1slot1_5 xxh 0276h can1 message slot buffer 1 data 0 c1slot1_6 xxh 0277h can1 message slot buffer 1 data 1 c1slot1_7 xxh 0278h can1 message slot buffer 1 data 2 c1slot1_8 xxh 0279h can1 message slot buffer 1 data 3 c1slot1_9 xxh 027ah can1 message slot buffer 1 data 4 c1slot1_10 xxh 027bh can1 message slot buffer 1 data 5 c1slot1_11 xxh 027ch can1 message slot buffer 1 data 6 c1slot1_12 xxh 027dh can1 message slot buffer 1 data 7 c1slot1_13 xxh 027eh can1 message slot buffer 1 time stamp high-order c1slot1_14 xxh 027fh can1 message slot buffer 1 time stamp low-order c1slot1_15 xxh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 38 of 85 table 4.12 sfr address map (12/20) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. the banksel bit in the c0ctlr1 register ca n switch functions for addresses 02a0h to 02bfh. 2. values are obtained by setting the sleep bit in the c1slpr register to ?1? (sleep mode exited) after reset and supplying a cl ock to the can module. 3. the can-associated registers (allocated in addresses 01e0h to 02 bfh) cannot be used in m32c/87b. in m32c/87a, only can0-assoc iated registers can be used. 4. set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers. address register (3)(4) symbol after reset 0280h can1 control register 0 c1ctlr0 xx01 0x01b (2) 0281h xxxx 0000b (2) 0282h can1 status register c1str 0000 0000b (2) 0283h x000 0x01b (2) 0284h can1 extended id register c1idr 0000h (2) 0285h 0286h can1 configuration register c1conr 0000 xxxxb (2) 0287h 0000 0000b (2) 0288h can1 time stamp register c1tsr 0000h (2) 0289h 028ah can1 transmit error count register c1tec 00h (2) 028bh can1 receive error count register c1rec 00h (2) 028ch can1 slot interrupt status register c1sistr 0000h (2) 028dh 028eh 028fh 0290h can1 slot interrupt mask register c1simkr 0000h (2) 0291h 0292h 0293h 0294h can1 error interrupt mask register c1eimkr xxxx x000b (2) 0295h can1 error interrupt status register c1eistr xxxx x000b (2) 0296h can1 error source register c1efr 00h (2) 0297h can1 baud rate prescaler c1brp 0000 0001b (2) 0298h 0299h can1 mode register c1mdr xxxx xx00b (2) 029ah 029bh 029ch 029dh 029eh 029fh 02a0h can1 single shot control register c1ssctlr 0000h (1)(2) 02a1h 02a2h 02a3h 02a4h can1 single shot status register c1ssstr 0000h (1)(2) 02a5h 02a6h 02a7h 02a8h can1 global mask register standard id0 c1gmr0 xxx0 0000b (1)(2) 02a9h can1 global mask register standard id1 c1gmr1 xx00 0000b (1)(2) 02aah can1 global mask register extended id0 c1gmr2 xxxx 0000b (1)(2) 02abh can1 global mask register extended id1 c1gmr3 00h (1)(2) 02ach can1 global mask register extended id2 c1gmr4 xx00 0000b (1)(2) 02adh 02aeh 02afh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 39 of 85 table 4.13 sfr address map (13/20) x: undefined blank spaces are all rese rved. no access is allowed. notes: 1. the banksel bit in the c1ctlr1 register ca n switch functions for addresses 02a0h to 02bfh. 2. values are obtained by setting the sleep bit in the c1slpr register to ?1? (sleep mode exited) after reset and supplying a cl ock to the can module. 3. the can-associated registers (allocated in addresses 01e0h to 02 bfh) cannot be used in m32c/87b. in m32c/87a, only can0-assoc iated registers can be used. 4. set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers. address register (3)(4) symbol after reset 02b0h can1 message slot 0 control register / can1 local mask register a standard id0 c1mctl0 / c1lmar0 0000 0000b (1)(2) / xxx0 0000b (1)(2) 02b1h can1 message slot 1 control register / can1 local mask register a standard id1 c1mctl1 / c1lmar1 0000 0000b (1)(2) / xx00 0000b (1)(2) 02b2h can1 message slot 2 control register / can1 local mask register a extended id0 c1mctl2 / c1lmar2 0000 0000b (1)(2) / xxxx 0000b (1)(2) 02b3h can1 message slot 3 control register / can1 local mask register a extended id1 c1mctl3 / c1lmar3 00h (1)(2) / 00h (1)(2) 02b4h can1 message slot 4 control register / can1 local mask register a extended id2 c1mctl4 / c1lmar4 0000 0000b (1)(2) / xx00 0000b (1)(2) 02b5h can1 message slot 5 control register c1mctl5 00h (1)(2) 02b6h can1 message slot 6 control register c1mctl6 00h (1)(2) 02b7h can1 message slot 7 control register c1mctl7 00h (1)(2) 02b8h can1 message slot 8 control register / can1 local mask register b standard id0 c1mctl8 / c1lmbr0 0000 0000b (1)(2) / xxx0 0000b (1)(2) 02b9h can1 message slot 9 control register / can1 local mask register b standard id1 c1mctl9 / c1lmbr1 0000 0000b (1)(2) / xx00 0000b (1)(2) 02bah can1 message slot 10 control register / can1 local mask register b extended id0 c1mctl10 / c1lmbr2 0000 0000b (1)(2) / xxxx 0000b (1)(2) 02bbh can1 message slot 11 control register / can1 local mask register b extended id1 c1mctl11 / c1lmbr3 00h (1)(2) / 00h (1)(2) 02bch can1 message slot 12 control register / can1 local mask register b extended id2 c1mctl12 / c1lmbr4 0000 0000b (1)(2) / xx00 0000b (1)(2) 02bdh can1 message slot 13 control register c1mctl13 00h (1)(2) 02beh can1 message slot 14 control register c1mctl14 00h (1)(2) 02bfh can1 message slot 15 control register c1mctl15 00h (1)(2)
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 40 of 85 table 4.14 sfr address map (14/20) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 02c0h x0 register, y0 register x0r, y0r xxxxh 02c1h 02c2h x1 register, y1 register x1r , y1r xxxxh 02c3h 02c4h x2 register, y2 register x2r , y2r xxxxh 02c5h 02c6h x3 register, y3 register x3r , y3r xxxxh 02c7h 02c8h x4 register, y4 register x4r , y4r xxxxh 02c9h 02cah x5 register, y5 register x5r , y5r xxxxh 02cbh 02cch x6 register, y6 register x6r , y6r xxxxh 02cdh 02ceh x7 register, y7 register x7r , y7r xxxxh 02cfh 02d0h x8 register, y8 register x8r , y8r xxxxh 02d1h 02d2h x9 register, y9 register x9r , y9r xxxxh 02d3h 02d4h x10 register, y10 register x10r , y10r xxxxh 02d5h 02d6h x11 register, y11 register x11r , y11r xxxxh 02d7h 02d8h x12 register, y12 register x12r , y12r xxxxh 02d9h 02dah x13 register, y13 register x13r , y13r xxxxh 02dbh 02dch x14 register, y14 register x14r , y14r xxxxh 02ddh 02deh x15 register, y15 register x15r , y15r xxxxh 02dfh 02e0h x/y control register xyc xxxx xx00b 02e1h 02e2h 02e3h 02e4h uart1 special mode register 4 u1smr4 00h 02e5h uart1 special mode register 3 u1smr3 00h 02e6h uart1 special mode register 2 u1smr2 00h 02e7h uart1 special mode register u1smr 00h 02e8h uart1 transmit/receive mode register u1mr 00h 02e9h uart1 baud rate register u1brg xxh 02eah uart1 transmit buffer register u1tb xxxxh 02ebh 02ech uart1 transmit/receive control register 0 u1c0 0000 1000b 02edh uart1 transmit/receive control register 1 u1c1 0000 0010b 02eeh uart1 receive buffer register u1rb xxxxh 02efh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 41 of 85 table 4.15 sfr address map (15/20) x: undefined blank spaces are all reserved. no access is allowed. note: 1. the ifsra register is included in the 144-pin package only. address register symbol after reset 02f0h 02f1h 02f2h 02f3h 02f4h uart4 special mode register 4 u4smr4 00h 02f5h uart4 special mode register 3 u4smr3 00h 02f6h uart4 special mode register 2 u4smr2 00h 02f7h uart4 special mode register u4smr 00h 02f8h uart4 transmit/receive mode register u4mr 00h 02f9h uart4 baud rate register u4brg xxh 02fah uart4 transmit buffer register u4tb xxxxh 02fbh 02fch uart4 transmit/receive control register 0 u4c0 0000 1000b 02fdh uart4 transmit/receive control register 1 u4c1 0000 0010b 02feh uart4 receive buffer register u4rb xxxxh 02ffh 0300h timer b3, b4, b5 count start register tbsr 000x xxxxb 0301h 0302h timer a11 register ta11 xxxxh 0303h 0304h timer a21 register ta21 xxxxh 0305h 0306h timer a41 register ta41 xxxxh 0307h 0308h three-phase pwm control register 0 invc0 00h 0309h three-phase pwm control register 1 invc1 00h 030ah three-phase output buffer register 0 idb0 xx11 1111b 030bh three-phase output buffer register 1 idb1 xx11 1111b 030ch dead time timer dtt xxh 030dh timer b2 interrupt generation frequency set counter ictb2 xxh 030eh 030fh 0310h timer b3 register tb3 xxxxh 0311h 0312h timer b4 register tb4 xxxxh 0313h 0314h timer b5 register tb5 xxxxh 0315h 0316h 0317h 0318h 0319h 031ah 031bh timer b3 mode register tb3mr 00xx 0000b 031ch timer b4 mode register tb4mr 00xx 0000b 031dh timer b5 mode register tb5mr 00xx 0000b 031eh external interrupt source select register 1 (1) ifsra 00h 031fh external interrupt source select register ifsr 00h
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 42 of 85 table 4.16 sfr address map (16/20) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0320h 0321h 0322h 0323h 0324h uart3 special mode register 4 u3smr4 00h 0325h uart3 special mode register 3 u3smr3 00h 0326h uart3 special mode register 2 u3smr2 00h 0327h uart3 special mode register u3smr 00h 0328h uart3 transmit/receive mode register u3mr 00h 0329h uart3 baud rate register u3brg xxh 032ah uart3 transmit buffer register u3tb xxxxh 032bh 032ch uart3 transmit/receive control register 0 u3c0 0000 1000b 032dh uart3 transmit/receive control register 1 u3c1 0000 0010b 032eh uart3 receive buffer register u3rb xxxxh 032fh 0330h 0331h 0332h 0333h 0334h uart2 special mode register 4 u2smr4 00h 0335h uart2 special mode register 3 u2smr3 00h 0336h uart2 special mode register 2 u2smr2 00h 0337h uart2 special mode register u2smr 00h 0338h uart2 transmit/receive mode register u2mr 00h 0339h uart2 baud rate register u2brg xxh 033ah uart2 transmit buffer register u2tb xxxxh 033bh 033ch uart2 transmit/receive control register 0 u2c0 0000 1000b 033dh uart2 transmit/receive control register 1 u2c1 0000 0010b 033eh uart2 receive buffer register u2rb xxxxh 033fh 0340h count start register tabsr 00h 0341h clock prescaler reset register cpsrf 0xxx xxxxb 0342h one-shot start register onsf 00h 0343h trigger select register trgsr 00h 0344h up/down select register udf 00h 0345h 0346h timer a0 register ta0 xxxxh 0347h 0348h timer a1 register ta1 xxxxh 0349h 034ah timer a2 register ta2 xxxxh 034bh 044ch timer a3 register ta3 xxxxh 034dh 034eh timer a4 register ta4 xxxxh 034fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 43 of 85 table 4.17 sfr address map (17/20) x: undefined blank spaces are all reserved. no access is allowed. note: 1. the tcspr register maintains values set before reset, even after software reset or watchdog timer reset has been performed. address register symbol after reset 0350h timer b0 register tb0 xxxxh 0351h 0352h timer b1 register tb1 xxxxh 0353h 0354h timer b2 register tb2 xxxxh 0355h 0356h timer a0 mode register ta0mr 00h 0357h timer a1 mode register ta1mr 00h 0358h timer a2 mode register ta2mr 00h 0359h timer a3 mode register ta3mr 00h 035ah timer a4 mode register ta4mr 00h 035bh timer b0 mode register tb0mr 00xx 0000b 035ch timer b1 mode register tb1mr 00xx 0000b 035dh timer b2 mode register tb2mr 00xx 0000b 035eh timer b2 special mode register tb2sc xxxx xxx0b 035fh count source prescaler register (1) tcspr 0xxx 0000b 0360h 0361h 0362h 0363h 0364h uart0 special mode register 4 u0smr4 00h 0365h uart0 special mode register 3 u0smr3 00h 0366h uart0 special mode register 2 u0smr2 00h 0367h uart0 special mode register u0smr 00h 0368h uart0 transmit/receive mode register u0mr 00h 0369h uart0 baud rate register u0brg xxh 036ah uart0 transmit buffer register u0tb xxxxh 036bh 036ch uart0 transmit/receive control register 0 u0c0 0000 1000b 036dh uart0 transmit/receive control register 1 u0c1 0000 0010b 036eh uart0 receive buffer register u0rb xxxxh 036fh 0370h 0371h 0372h irda control register ircon x000 0000b 0373h 0374h 0375h 0376h 0377h 0378h dma0 request source select register dm0sl 0x00 0000b 0379h dma1 request source select register dm1sl 0x00 0000b 037ah dma2 request source select register dm2sl 0x00 0000b 037bh dma3 request source select register dm3sl 0x00 0000b 037ch crc data register crcd xxxxh 037dh 037eh crc input register crcin xxh 037fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 44 of 85 table 4.18 sfr address map (18/20) x: undefined blank spaces are all reserved. no access is allowed. address register symbol after reset 0380h a/d0 register 0 ad00 00xxh 0381h 0382h a/d0 register 1 ad01 00xxh 0383h 0384h a/d0 register 2 ad02 00xxh 0385h 0386h a/d0 register 3 ad03 00xxh 0387h 0388h a/d0 register 4 ad04 00xxh 0389h 038ah a/d0 register 5 ad05 00xxh 038bh 038ch a/d0 register 6 ad06 00xxh 038dh 038eh a/d0 register 7 ad07 00xxh 038fh 0390h 0391h 0392h a/d0 control register 4 ad0con4 xxxx 00xxb 0393h 0394h a/d0 control register 2 ad0con2 xx0x x000b 0395h a/d0 control register 3 ad0con3 xxxx x000b 0396h a/d0 control register 0 ad0con0 00h 0397h a/d0 control register 1 ad0con1 00h 0398h d/a register 0 da0 xxh 0399h 039ah d/a register 1 da1 xxh 039bh 039ch d/a control register dacon xxxx xx00b 039dh d/a control register 1 dacon1 xxxx 0000b 039eh 039fh
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 45 of 85 table 4.19 sfr address map (19/20) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. these registers cannot be used in the 100-pin package. 2. set to ffh in the 100-pin package. address register symbol after reset 03a0h function select register a8 (1) ps8 x000 0000b 03a1h function select register a9 (1) ps9 00h 03a2h 03a3h function select register b9 (1) psl9 xxx0 xx00b 03a4h function select register e2 pse2 xxxx xx0xb 03a5h 03a6h 03a7h function select register d1 psd1 00x0 xx00b 03a8h function select register d2 psd2 xxxx xx0xb 03a9h 03aah function select register c6 (1) psc6 xxxx 0x00b 03abh function select register e1 pse1 00xx xx00b 03ach function select register c2 psc2 xxxx x00xb 03adh function select register c3 psc3 x0xx xxxxb 03aeh 03afh function select register c psc 00h 03b0h function select register a0 ps0 00h 03b1h function select register a1 ps1 00h 03b2h function select register b0 psl0 00h 03b3h function select register b1 psl1 00h 03b4h function select register a2 ps2 00x0 0000b 03b5h function select register a3 ps3 00h 03b6h function select register b2 psl2 00x0 0000b 03b7h function select register b3 psl3 00h 03b8h function select register a4 ps4 00h 03b9h function select register a5 (1) ps5 xxx0 0000b 03bah 03bbh function select register b5 (1) psl5 xxx0 0000b 03bch function select register a6 (1) ps6 00h 03bdh function select register a7 (1) ps7 00h 03beh function select register b6 (1) psl6 00h 03bfh function select register b7 (1) psl7 00h 03c0h port p6 register p6 xxh 03c1h port p7 register p7 xxh 03c2h port p6 direction register pd6 00h 03c3h port p7 direction register pd7 00h 03c4h port p8 register p8 xxh 03c5h port p9 register p9 xxh 03c6h port p8 direction register pd8 00x0 0000b 03c7h port p9 direction register pd9 00h 03c8h port p10 register p10 xxh 03c9h port p11 register (1) p11 xxh 03cah port p10 direction register pd10 00h 03cbh port p11 direction register (1)(2) pd11 xxx0 0000b 03cch port p12 register (1) p12 xxh 03cdh port p13 register (1) p13 xxh 03ceh port p12 direction register (1)(2) pd12 00h 03cfh port p13 direction register (1)(2) pd13 00h
m32c/87 group (m32c/87, m32c/87a, m32c/87b ) 4. special function registers (sfrs) rej03b0127-0151 rev.1.51 jul 31, 2008 page 46 of 85 table 4.20 sfr address map (20/20) x: undefined blank spaces are all reserved. no access is allowed. notes: 1. these registers cannot be used in the 100-pin package. 2. set to ffh in the 100-pin package. 3. set to 00h in the 100-pin package. address register symbol after reset 03d0h port p14 register (1) p14 xxh 03d1h port p15 register (1) p15 xxh 03d2h port p14 direction register (1)(2) pd14 x000 0000b 03d3h port p15 direction register (1)(2) pd15 00h 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah pull-up control register 2 pur2 00h 03dbh pull-up control register 3 pur3 00h 03dch pull-up control register 4 (1)(3) pur4 xxxx 0000b 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech 03edh 03eeh 03efh 03f0h pull-up control register 0 pur0 00h 03f1h pull-up control register 1 pur1 xxxx 0000b 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh port control register pcr xxxx x000b
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 47 of 85 5. electrical characteristics table 5.1 absolute maximum ratings notes: 1. p11 to p15 are provided in the 144-pin package only. 2. contact a renesas sales office if temperature range of -40 to 85 c is required. symbol parameter condition value unit vcc1, vcc2 supply voltage vcc1 = avcc -0.3 to 6.0 v vcc2 supply voltage ? -0.3 to vcc1 + 0.1 v avcc analog supply voltage vcc1 = avcc -0.3 to 6.0 v vi input voltage reset , cnvss, byte, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) , vref, xin -0.3 to vcc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) -0.3 to vcc2 + 0.3 p7_0, p7_1 -0.3 to 6.0 vo output voltage p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p14_0 to 14_6, p15_0 to p15_7 (1) , xout -0.3 to vcc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) -0.3 to vcc2 + 0.3 p7_0, p7_1 -0.3 to 6.0 pd power consumption -40 c topr 85 c 500 mw topr operating ambient temperature during cpu operation -20 to 85/ -40 to 85 (2) c during programming or erasing flash memory 0 to 60 c tstg storage temperature -65 to 150 c
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 48 of 85 table 5.2 recommended operating conditions (1/3) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified) notes: 1. vih and vil reference for p8_7 apply when p8_7 is us ed as a programmable input port. it does not apply when p8_7 is used as xcin. 2. p11 to p15 are provided in the 144-pin package only. symbol parameter standard unit min. typ. max. vcc1, vcc2 supply voltage (vcc1 vcc2) 3.0 5.0 5.5 v avcc analog supply voltage vcc1 v vss supply voltage 0 v avss analog supply voltage 0 v vih input high ?h? voltage p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (2) 0.8vcc2 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7 (1) , p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (2) , xin, reset , cnvss, byte 0.8vcc1 vcc1 p7_0, p7_1 0.8vcc1 6.0 p0_0 to p0_7, p1_0 to p1_7 (in single-chip mode) 0.8vcc2 vcc2 p0_0 to p0_7, p1_0 to p1_7 (in memory expansion mode and microprocessor mode) 0.5vcc2 vcc2 vil input low ?l? voltage p2_0 to p2_7,p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (2) 0 0.2vcc2 v p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (1) , p9_0 to p9_7, p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (2) , xin, reset , cnvss, byte 0 0.2vcc1 p0_0 to p0_7, p1_0 to p1_7 (in single-chip mode) 0 0.2vcc2 p0_0 to p0_7, p1_0 to p1_7 (in memory expansion mode and microprocessor mode) 0 0.16vcc2
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 49 of 85 table 5.3 recommended operating conditions (2/3) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified notes: 1. average output current is the average value within 100 ms. 2. a total iol(peak) of p0, p1, p2, p8_6, p8_7, p9, p10 , p11, p14, and p15 must be 80 ma or less. a total iol(peak) of p3, p4, p5, p6, p7,p8_0 to p8_4, p12, and p13 must be 80 ma or less. a total ioh(peak) of p0, p1, p2, and p11 must be -40 ma or less. a total ioh(peak) of p8_6 to p8_7, p9, p 10, p14, and p15 must be -40 ma or less. a total ioh(peak) of p3, p4, p5, p12, and p13 must be -40 ma or less. a total ioh(peak) of p6, p7, and p8_0 to p8_4 must be -40 ma or less. 3. p11 to p15 are provided in the 144-pin package only. symbol parameter standard unit min. typ. max. ioh(peak) peak output high ?h? current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) -10.0 ma ioh(avg) average output high ?h? current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) -5.0 ma iol(peak) peak output low ?l? current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) 10.0 ma iol(avg) average output low ?l? current (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (3) 5.0 ma
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 50 of 85 table 5.4 recommended operating conditions (3/3) (vcc1 = vcc2 = 3.0 to 5.5 v, topr = -20 to 85 c unless otherwise specified) symbol parameter standard unit min. typ. max. f(cpu) cpu clock frequency (same frequency as f(bclk)) vcc1 = 4.2 to 5.5v 0 32 mhz vcc1 = 3.0 to 5.5v 0 24 mhz f(xin) main clock input oscillation frequency vcc1 = 4.2 to 5.5v 0 32 mhz vcc1 = 3.0 to 5.5v 0 24 mhz f(xcin) sub clock frequency 32.768 50 khz f(ring) on-chip oscillator frequency 1 mhz f(vco) vco clock frequency (pll frequency synthesizer) 20 80 mhz f(pll) pll clock frequency vcc1 = 4.2 to 5.5v 10 32 mhz vcc1 = 3.0 to 5.5v 10 24 mhz tsu(pll) wait time to stabilize pll frequency synthesizer vcc1 = 5.0v 5 ms vcc1 = 3.3v 10 ms
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 51 of 85 table 5.5 electrical characteristics (1/3) (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 32 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter measurement condition standard unit min. typ. max. voh output high ?h? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -5 ma vcc2 - 2.0 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) ioh = -5 ma vcc1 - 2.0 vcc1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7 p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -200 a vcc2 - 0.3 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) ioh = -200 a vcc1 - 0.3 vcc1 xout ioh = -1 ma 3.0 vcc1 v xcout drive capability = high no load applied 2.5 v drive capability = low no load applied 1.6 v vol output low ?l? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 200 a0.45v xout iol = 1 ma 2.0 v xcout drive capability = high no load applied 0v drive capability = low no load applied 0v vt+ - vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int 8 , adtrg , cts0 to cts 6 , clk0 to clk6, ta0out to ta4out, nmi , ki0 to ki3 , rxd0 to rxd6, scl0 to scl4, sda0 to sda4, inpc1_0 to inpc1_7, isclk0 to isclk2, isrxd0 to isrxd2, iein, can0in, can1in, can1wu 0.2 1.0 v reset 0.2 1.8 v vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 52 of 85 table 5.6 electrical characteristics (2/3) (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 32 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter measurement condition standard unit min. typ. max. iih input high ?h? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 5 v 5.0 a iil input low ?l? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 0v -5.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) vi = 0v 30 50 167 k rfxin feedback resistance xin 1.5 m rfxcin feedback resistance xcin 10 m vram ram data retention voltage in stop mode 2.0 v vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 53 of 85 table 5.7 electrical characteristics (3/3) (vcc1 = vcc2 = 5.5 v, vss = 0 v, topr = 25 c ) notes: 1. in single-chip mode, leave the output pins open and connect the input pins to vss. 2. value is obtained when setting the fmstp bit in the fmr0 register to 1 (flash memory stopped) and running the program on ram. symbol parameter mea surement condition (1) standard unit min. typ. max. icc power supply current flash memory version f(cpu) = 32 mhz 32 45 ma f(cpu) = 16 mhz 19 ma f(cpu) = 8 mhz 12 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 2.6 ma f(cpu) = 32 khz in low-power consumption mode while flash memory is operating 430 a f(cpu) = 32 khz in low-power consumption mode while flash memory is stopped (2) 30 a wait mode: f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 50 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a mask rom version f(cpu) = 32 mhz 32 45 ma f(cpu) = 16 mhz 19 ma f(cpu) = 8 mhz 12 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 1ma f(cpu) = 32 khz in low-power consumption mode 30 a wait mode: f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 50 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 54 of 85 table 5.8 a/d conversion characteristics (vcc1 = vcc2 = avcc = vref = 4.2 to 5. 5 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 32mhz unless otherwise specified) notes: 1. the value is obtained when ad frequency is at 16 mhz. keep ad frequency at 16 mhz or lower. 2. with using the sample and hold function table 5.9 d/a conversion characteristics (vcc1 = vcc2 = vref = 4.2 to 5.5 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 32mhz unless otherwise specified) note: 1. measured when one d/a converter is used, and the dai regist er (i = 0, 1) of the unused d/a converter is set to 00h. the current flown into the resist or ladder in the a/d converter is excl uded. ivref flows even if the vcut bit in the ad0con1 register is set to 0 (vref not connected) symbol parameter measurement condition standard unit min. typ. max. ? resolution vref = vcc1 10 bits inl integral nonlinearity error vref = vcc1 = vcc2 = 5 v an_0 to an_7, an0_0 to an0_7, an2_0 to an2_7, an15_0 to an15_7, anex0, anex1 3 lsb external op-amp connection mode 7 lsb dnl differential nonlinearity error 1 lsb ? offset error 3 lsb ? gain error 3 lsb rladder resistor ladder vref = vcc1 8 40 k tconv 10-bit conversion time (1)(2) 2.06 s tconv 8-bit conversion time (1)(2) 1.75 s tsamp sampling time (1) 0.188 s vref reference voltage 2 vcc1 v via analog input voltage 0 vref v symbol parameter measurement condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % tsu setup time 3 s ro output resistance 4 10 20 k ivref reference power supply input current (note 1) 1.5 ma vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 55 of 85 table 5.10 flash memory electrical characteristi cs (vcc1 = 4.5 v to 5.5 v, 3.0 to 3.6 v, topr = 0 to 60 c unless otherwise specified) note: 1. if erase and program endurance is n times (n = 100), each block can be erased n times. for example, if a 4- kbyte block a is erased after programming a word data 2,048 times, each to a different address, this counts as one erase and program time. data can not be progr ammed to the same address more than once without erasing the block. (rewrite prohibited) symbol parameter measu rement condition standard unit min. typ. max. ? erase and program endurance (1) 100 times ? word program time (16 bits) (vcc1 = 5.0 v, topr = 25 c) 25 300 s ? lock bit program time 25 300 s ? block erase time (vcc1 = 5.0 v, topr = 25 c) 4-kbyte block 0.3 4 s 8-kbyte block 0.3 4 s 32-kbyte block 0.5 4 s 64-kbyte block 0.8 4 s tps wait time to stabilize flash memory circuit 15 s ? data hold time (topr = -40 to 85 c) 10 years vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 56 of 85 table 5.11 voltage detection circuit electrical characteristics (vcc1 = vcc2 = 3.0 to 5.5 v, vss = 0 v, topr = 25 c unless otherwise specified) notes: 1. vdet4 > vdet3 2. vdet3r > vdet3 is not guaranteed. table 5.12 power supply circuit timing characteristics note: 1. when vcc1 = 5 v figure 5.1 power supply timing diagram symbol parameter measu rement condition standard unit min. typ. max. vdet4 vdet4 detection voltage vcc1 = 3.0 v to 5.5 v 3.3 3.8 4.4 v vdet3 vdet3 detection voltage 3.0 v vdet3s hardware reset 2 hold voltage 2.0 v vdet3r hardware reset 2 release voltage 3.1 v symbol parameter measu rement condition standard unit min. typ. max. td(p-r) wait time to stabilize internal supply voltage when power-on vcc1 = 3.0 to 5.5 v 2 ms td(s-r) wait time to release hardwa re reset 2 vcc1 = vdet3r to 5.5 v 6 (1) 20 ms td(e-a) start-up time for vdet3 and vdet4 detection circuit vcc1 = 3.0 to 5.5 v 20 s td(p-r) vcc1 cpu clock recommended operating voltage td(p-r) wait time to stabilize internal supply voltage when power-on td(s-r) vcc1 cpu clock vdet3r td(s-r) wait time to release hardware reset 2 td(e-a) td(e-a) start-up time for vdet3 and vdet4 detection circuit vc26, vc27 vdet3 and vdet4 detection circuit stop operating vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 57 of 85 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.13 external clock input table 5.14 timer a input (count source input in event counter mode) i = 0 to 4 table 5.15 timer a input (gate signal input in timer mode) i = 0 to 4 table 5.16 timer a input (external trigger input in one-shot timer mode) i = 0 to 4 table 5.17 timer a input (external trigger input in pulse width modulation mode) i = 0 to 4 symbol parameter standard unit min. max. tc external clock input cycle time 31.25 ns tw(h) external clock input high (?h?) pulse width 13.75 ns tw(l) external clock input low (?l?) pulse width 13.75 ns tr external clock rise time 5 ns tf external clock fall time 5 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input high (?h?) pulse width 40 ns tw(tal) taiin input low (?l?) pulse width 40 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high (?h?) pulse width 200 ns tw(tal) taiin input low (?l?) pulse width 200 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns symbol parameter standard unit min. max. tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 58 of 85 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.18 timer a input (counter increment/ decrement input in event counter mode) i = 0 to 4 table 5.19 timer a input (two-phase pulse input in event counter mode) i = 0 to 4 table 5.20 timer b input (count source input in event counter mode) i = 0 to 5 table 5.21 timer b input (pulse period measurement mode) i = 0 to 5 table 5.22 timer b input (pulse width measurement mode) i = 0 to 5 symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high (?h?) pulse width 1000 ns tw(upl) taiout input low (?l?) pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 800 ns tsu(tain-taout) taiout input setup time 200 ns tsu(taout-tain) taiin input setup time 200 ns symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high (?h?) pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low (?l?) pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high (?h?) pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low (?l?) pulse width (counted on both edges) 80 ns symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 59 of 85 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.23 a/d trigger input table 5.24 serial interface i = 0 to 6 table 5.25 intelligent i/o communication function (groups 0 and 1) i = 0, 1 table 5.26 intelligent i/o communication function (group 2) symbol parameter standard unit min. max. tc(ad) adtrg input cycle time (required for trigger) 1000 ns tw(adl) adtrg input low (?l?) pulse width 125 ns symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high (?h?) pulse width 100 ns tw(ckl) clki input low (?l?) pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi output hold time 0 ns tsu(d-c) rxdi input setup time 70 ns th(c-d) rxdi input hold time 90 ns symbol parameter standard unit min. max. tc(ck) isclki input cycle time 600 ns tw(ckh) isclki input high (?h?) pulse width 300 ns tw(ckl) isclki input low (?l?) pulse width 300 ns td(c-q) istxdi output delay time 100 ns th(c-q) istxdi output hold time 0 ns tsu(d-c) isrxdi input setup time 100 ns th(c-d) isrxdi input hold time 100 ns symbol parameter standard unit min. max. tc(ck) isclk2 input cycle time 600 ns tw(ckh) isclk2 input high (?h?) pulse width 300 ns tw(ckl) isclk2 input low (?l?) pulse width 300 ns td(c-q) istxd2 output delay time 180 ns th(c-q) istxd2 output hold time 0 ns tsu(d-c) isrxd2 input setup time 150 ns th(c-d) isrxd2 input hold time 100 ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 60 of 85 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.27 external interrupt inti input (edge sensitive) i = 0 to 8 (1) note: 1. int6 to int8 are provided in the 144-pin package only. symbol parameter standard unit min. max. tw(inh) inti input high (?h?) pulse width 250 ns tw(inl) inti input low (?l?) pulse width 250 ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 61 of 85 timing requirements (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 q c unless otherwise specified) table 5.28 memory expansion mode and microprocessor mode note: 1. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. insert wait states or lower the operation frequency, f(bclk), if the calculated value is negative. 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a i + b i , m = (b 2) + 1) tac1(rd-db) = 10 9 n f(bclk) - 35 [ns] (if external bus cycle is a i + b i , n = a + b) tac1(ad-db) = 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a i + b i , m = (b 2) - 1) tac2(rd-db) = 10 9 p f(bclk) 2 - 35 [ns] (if external bus cycle is a i + b i , p = {(a + b - 1) 2} + 1) tac2(ad-db) = symbol parameter standard unit min. max. tac1(rd-db) data input access time (rd standard) (note 1) ns tac1(ad-db) data input access time (ad standard, cs standard) (note 1) ns tac2(rd-db) data input access time (rd standar d, when accessing a space with the multiplexed bus) (note 1) ns tac2(ad-db) data input access time (ad standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(db-bclk) data input setup time 26 ns tsu(rdy-bclk) rdy input setup time 26 ns tsu(hold-bclk) hold input setup time 30 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns td(bclk-hlda) hlda output delay time 25 ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 62 of 85 switching characteristics (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 q c unless otherwise specified) table 5.29 memory expansion mode and micr oprocessor mode (when accessing external memory space) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 10 9 f(bclk) 2 - 15 [ns] th(wr-db) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. 10 9 n f(bclk) 2 - 15 [ns] (if external bus cycle is a i + b i , n = (b 2) - 1) tw(wr) = 10 9 m f(bclk) - 20 [ns] (if external bus cycle is a i + b i , m = b) td(db-wr) = 3. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (3) 0 ns th(wr-ad) address output hold time (wr standard) (3) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (3) 0 ns th(wr-cs) chip-select signal output hold time (wr standard) (3) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time -5 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (3) (note 1) ns tw(wr) wr output width (note 2) ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 63 of 85 switching characteristics (vcc1 = vcc2 = 4.2 to 5.5 v, vss = 0 v, topr = -20 to 85 q c unless otherwise specified) table 5.30 memory expansion mode and microprocessor mode (when accessing external memory space with multiplexed bus) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 10 9 f(bclk) 2 - 10 [ns] th(rd-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(rd-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 f(bclk) 2 - 15 [ns] th(wr-db) = 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 10 9 m f(bclk) 2 - 25 [ns] (if external bus cycle is a i + b i , m = (b 2) - 1) td(db-wr) = 3. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a i + b i , n = a) td(ad-ale) = 4. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a i + b i , n = a) th(ale-ad) = 5. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (5) (note 1) ns th(wr-ad) address output hold time (wr standard) (5) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (5) (note 1) ns th(wr-cs) chip-select signal output hold time (wr standard) (5) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time -5 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (5) (note 1) ns td(bclk-ale) ale signal output delay time (bclk standard) 18 ns th(bclk-ale) ale signal output hold time (bclk standard) -2 ns td(ad-ale) ale signal output delay time (address standard) (note 3) ns th(ale-ad) ale signal output hold time (address standard) (note 4) ns tdz(rd-ad) address output float start time 8 ns vcc1 = vcc2 = 5v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 64 of 85 p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30 pf p11 p12 p13 p14 p15 note 1 note: 1. p11 to p15 are provided in the 144-pin package only. figure 5.2 p0 to p15 measurement circuit
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 65 of 85 figure 5.3 vcc1 = vcc2 = 5 v timing diagram (1/4) vcc1=vcc2=5v taiin input tc(ta) tw(tah) tw(tal) taiout input tc(up) tw(uph) tw(upl) taiout input (counter increment/ decrement select input) taiin input (count on falling edge) taiin input (count on rising edge) th(tin-up) tsu(up-tin) in event counter mode tbiin input tc(tb) tw(tbh) tw(tbl) adtrg input tc(ad) tw(adl) clki isclki tc(ck) tw(ckh) tw(ckl) txdi istxdi th(c-q) td(c-q) rxdi isrxdi tsu(d-c) th(c-d) inti input tw(inl) tw(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more ("l" width) xin input tc tw(l) tw(h) tr tf taiin input taiout input in event counter mode with two-phase pulse input tc(ta) tsu(tain-taout) tsu(tain-taout) tsu(taout-tain) tsu(taout-tain)
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 66 of 85 figure 5.4 vcc1 = vcc2 = 5 v timing diagram (2/4) memory expansion mode and microprocessor mode bclk rd (separate bus) wr, wrl, wrh (separate bus) rd (multiplexed bus) wr, wrl, wrh (multiplexed bus) rdy input tsu(rdy-bclk) th(bclk-rdy) hi-z tsu(hold-bclk) td(bclk-hlda) bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 measurement conditions - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage: vih = 4.0 v, vil = 1.0 v - output high and low voltage: voh = 2.5 v, vol = 2.5 v vcc1=vcc2=5v th(bclk-hold) td(bclk-hlda)
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 67 of 85 figure 5.5 vcc1 = vcc2 = 5 v timing diagram (3/4) vcc1=vcc2=5v memory expansion mode and microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the mcu is used stand-alone. a maximum of 35 ns is guaranteed for td(bclk-ad) + tsu(db-bclk). 2. varies with operation frequency: tac1(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) + 1) tac1(ad-db) = (tcyc x n - 35) ns.max (if external bus cycle a + b , n = a + b) read timing (1 + 1 bus cycle) write timing (1 + 1 bus cycle) notes: 3. varies with operation frequency: td(db-wr) = (tcyc x m - 20) ns.min ( if external bus cycle a + b , m = b) th(wr-db) = (tcyc / 2 - 15) ns.min th(wr-ad) = (tcyc / 2 - 10) ns.min th(wr-cs) = (tcyc / 2 - 10) ns.min tw(wr) = (tcyc / 2 x n - 15) ns.min (if external bus cycle a + b , n = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage: vih = 2.5 v, vil = 0.8 v - output high and low voltage: voh = 2.0 v, vol = 0.8 v tcyc= 10 9 f(bclk) bclk csi adi bhe dbi th(bclk-cs) -3ns.min td(bclk-cs) 18ns.max tcyc td(bclk-ad) 18ns.max th(wr-ad) (3) th(bclk-wr) -5ns.min td(db-wr) (3) th(bclk-ad) -3ns.min td(bclk-wr) 18ns.max tw(wr) (3) th(wr-db) (3) th(wr-cs) (3) wr,wrl,wrh bclk csi adi bhe rd dbi th(bclk-cs) -3ns.min th(rd-cs) 0ns.min td(bclk-cs) 18ns.max (1) tcyc td(bclk-ad) 18ns.max (1) 18ns.max td(bclk-rd) th(rd-ad) 0ns.min th(bclk-rd) -5ns.min tac1(rd-db) (2) tac1(ad-db) (2) hi-z th(rd-db) 0ns.min tsu(db-bclk) 26ns.min (1) th(bclk-ad) -3ns.min
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 68 of 85 figure 5.6 vcc1 = vcc2 = 5 v timing diagram (4/4) bclk csi adi bhe rd ale td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (1) th(ale-ad) (1) tdz(rd-ad) 8ns.max tac2(rd-db) (1) th(bclk-cs) -3ns.min th(rd-db) 0ns.min th(bclk-ad) -3ns.min td(bclk-ad) 18ns.max adi /dbi td(bclk-rd) 18ns.max tac2(ad-db) (1) th(bclk-rd) -5ns.min th(rd-ad) (1) tcyc address notes: 1. varies with operation frequency: td(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(ale-ad) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(rd-ad) = (tcyc / 2 - 10) ns.min, th(rd-cs) = (tcyc / 2 - 10) ns.min tac2(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) - 1) tac2(ad-db) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b , p = {(a + b - 1) x 2} + 1) notes: 1. varies with operation frequency: td(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(ale-ad) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(wr-ad) = (tcyc / 2 - 10) ns.min, th(wr-cs) = (tcyc / 2 - 10) ns.min th(wr-db) = (tcyc / 2 - 15) ns.min td(db-wr) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b , m = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 4.2 to 5.5 v - input high and low voltage vih = 2.5 v, vil = 0.8 v - output high and low voltage voh = 2.0 v, vol = 0.8 v address vcc1=vcc2=5v memory expansion mode and microprocessor mode (when accessing an external memory space with the multiplexed bus) read timing (2 + 2 bus cycle) tcyc= 10 9 f(bclk) bclk csi adi bhe wr,wrl,wrh write timing (2 + 2 bus cycle) td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (2) th(ale-ad) (2) td(db-wr) (2) th(wr-cs) (2) td(bclk-ad) 18ns.max td(bclk-wr) 18ns.max th(bclk-wr) -5ns.min tcyc address data output th(wr-db) (2) adi /dbi ale address th(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min th(rd-cs) (1) data input tsu(db-bclk) 26ns.min th(wr-ad) (2)
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 69 of 85 table 5.31 electrical characteristics (1/3) (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 24 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter measurement condition standard unit min. typ. max. voh output high ?h? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7 (1) ioh = -1 ma vcc2 - 0.6 vcc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p14_0 to p14_6, p15_0 to p15_7 (1) vcc1 - 0.6 vcc1 xout ioh = -0.1 ma 2.7 vcc1 v xcout drive capability = high no load applied 2.5 v drive capability = low no load applied 1.6 v vol output low ?l? voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) iol = 1 ma 0.5 v xout iol = 0.1 ma 0.5 v xcout drive capability = high no load applied 0v drive capability = low no load applied 0v vt+ - vt- hysteresis hold , rdy , ta0in to ta4in, tb0in to tb5in, int0 to int 8 , adtrg , cts0 to cts 6 , clk0 to clk6, ta0out to ta4out, nmi , ki0 to ki3 , rxd0 to rxd6, scl0 to scl4, sda0 to sda4, inpc1_0 to inpc1_7, isclk0 to isclk2, isrxd0 to isrxd2, iein, can0in, can1in, can1wu 0.2 1.0 v reset 0.2 1.8 v vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 70 of 85 table 5.32 electrical characteristics (2/3) (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c, f(cpu) = 24 mhz unless otherwise specified) note: 1. p11 to p15 are provided in the 144-pin package only. symbol parameter measurement condition standard unit min. typ. max. iih input high ?h? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 3 v 4.0 a iil input low ?l? current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) , xin, reset , cnvss, byte vi = 0v -4.0 a rpullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7,p10_0 to p10_7, p11_0 to p11_4, p12_0 to p12_7, p13_0 to p13_7, p14_0 to p14_6, p15_0 to p15_7 (1) vi=0v 40 90 500 k rfxin feedback resistance xin 3.0 m rfxcin feedback resistance xcin 20.0 m vram ram data retention voltage in stop mode 2.0 v vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 71 of 85 table 5.33 electrical characteristics (3/3) (vcc1 = vcc2 = 3.3 v, vss = 0 v, topr = 25 c) notes: 1. in single-chip mode, leave the output pins open and connect the input pins to vss. 2. value is obtained when setting the fmstp bit in the fmr0 register to 1 (flash memory stopped) and running the program on ram. symbol parameter mea surement condition (1) standard unit min. typ. max. icc power supply current flash memory version f(cpu) = 24 mhz 23 33 ma f(cpu) = 16 mhz 17 ma f(cpu) = 8 mhz 11 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 2.6 ma f(cpu) = 32 khz in low-power consumption mode while flash memory is operating 430 a f(cpu) = 32 khz in low-power consumption mode while flash memory is stopped (2) 30 a wait mode: f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 45 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a mask rom version f(cpu) = 24 mhz 23 33 ma f(cpu) = 16 mhz 17 ma f(cpu) = 8 mhz 11 ma f(cpu) = f(ring) in on-chip oscillator low-power consumption mode 1ma f(cpu) = 32 khz in low-power consumption mode 30 a wait mode: f(cpu) = f(ring) after entering wait mode from on-chip oscillator low-power consumption mode 45 a stop mode (while clock is stopped) 0.8 5 a stop mode (while clock is stopped) topr = 85 c50 a vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 72 of 85 table 5.34 a/d conversion characteristics (vcc1 = vcc2 = avcc = vref = 3.0 to 3. 6 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 24mhz unless otherwise specified) notes: 1. the value when ad frequency is at 10 mhz. keep ad frequency at 10 mhz or lower. if f(cpu) (=fad) is 24 mhz, divide f(cpu) by 3 to make it 8 mhz. the conversion time in this case is 6.1 s. 2. sample and hold function is not available. table 5.35 d/a conversion characteristics (vcc1 = vcc2 = vref = 3.0 to 3.6 v, vss = avss = 0 v, topr = -20 to 85 c, f(cpu) = 24mhz unless otherwise specified) note: 1. measurement when one d/a converter is used, and the dai register (i = 0, 1) of the unused d/a converter is set to 00h. the current flown into the resistor ladder in th e a/d converter is excluded. ivref flows even if vcut bit in the ad0con1 register is set to 0 (vref not connected) symbol parameter measurement condition standard unit min. typ. max. ? resolution vref = vcc1 10 bits inl integral nonlinearity error (8-b it) vref = vcc1 = vcc2 = 3.3 v 2 lsb dnl differential nonlinearity error (8-bit) 1 lsb ? offset error (8-bit) 2 lsb ? gain error (8-bit) 2 lsb rladder resistor ladder vref = vcc1 8 40 k tconv 8-bit conversion time (1)(2) 4.9 s vref reference voltage 3 vcc1 v via analog input voltage 0 vref v symbol parameter measurement condition standard unit min. typ. max. ? resolution 8bits ? absolute accuracy 1.0 % tsu setup time 3 s ro output resistance 4 10 20 k ivref reference power supply input current (note 1) 1.0 ma vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 73 of 85 timing requirements ( vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified ) table 5.36 external clock input table 5.37 timer a input (count source input in event counter mode) i = 0 to 4 table 5.38 timer a input (gate signal input in timer mode) i = 0 to 4 table 5.39 timer a input (external trigger input in one-shot timer mode) i = 0 to 4 table 5.40 timer a input (external trigger input in pulse width modulation mode) i = 0 to 4 symbol parameter standard unit min. max. tc external clock input cycle time 41 ns tw(h) external clock input high (?h?) pulse width 18 ns tw(l) external clock input low (?l?) pulse width 18 ns tr external clock rise time 5 ns tf external clock fall time 5 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 100 ns tw(tah) taiin input high (?h?) pulse width 40 ns tw(tal) taiin input low (?l?) pulse width 40 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 400 ns tw(tah) taiin input high (?h?) pulse width 200 ns tw(tal) taiin input low (?l?) pulse width 200 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 200 ns tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns symbol parameter standard unit min. max. tw(tah) taiin input high (?h?) pulse width 100 ns tw(tal) taiin input low (?l?) pulse width 100 ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 74 of 85 timing requirements ( vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified ) table 5.41 timer a input (counter increment/ decrement input in event counter mode) i = 0 to 4 table 5.42 timer a input (two-phase pulse input in event counter mode) i = 0 to 4 table 5.43 timer b input (count source input in event counter mode) i = 0 to 5 table 5.44 timer b input (pulse period measurement mode) i = 0 to 5 table 5.45 timer b input (pulse width measurement mode) i = 0 to 5 symbol parameter standard unit min. max. tc(up) taiout input cycle time 2000 ns tw(uph) taiout input high (?h?) pulse width 1000 ns tw(upl) taiout input low (?l?) pulse width 1000 ns tsu(up-tin) taiout input setup time 400 ns th(tin-up) taiout input hold time 400 ns symbol parameter standard unit min. max. tc(ta) taiin input cycle time 2 s tsu(tain-taout) taiout input setup time 500 ns tsu(taout-tain) taiin input setup time 500 ns symbol parameter standard unit min. max. tc(tb) tbiin input cycle time (counted on one edge) 100 ns tw(tbh) tbiin input high (?h?) pulse width (counted on one edge) 40 ns tw(tbl) tbiin input low (?l?) pulse width (counted on one edge) 40 ns tc(tb) tbiin input cycle time (counted on both edges) 200 ns tw(tbh) tbiin input high (?h?) pulse width (counted on both edges) 80 ns tw(tbl) tbiin input low (?l?) pulse width (counted on both edges) 80 ns symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns symbol parameter standard unit min. max. tc(tb) tbiin input cycle time 400 ns tw(tbh) tbiin input high (?h?) pulse width 200 ns tw(tbl) tbiin input low (?l?) pulse width 200 ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 75 of 85 timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.46 a/d trigger input table 5.47 serial interface i = 0 to 6 table 5.48 intelligent i/o communication function (groups 0 and 1) i = 0, 1 table 5.49 intelligent i/o communication function (group 2) symbol parameter standard unit min. max. tc(ad) adtrg input cycle time (required for trigger) 1000 ns tw(adl) adtrg input low (?l?) pulse width 125 ns symbol parameter standard unit min. max. tc(ck) clki input cycle time 200 ns tw(ckh) clki input high (?h?) pulse width 100 ns tw(ckl) clki input low (?l?) pulse width 100 ns td(c-q) txdi output delay time 80 ns th(c-q) txdi output hold time 0 ns tsu(d-c) rxdi input setup time 70 ns th(c-d) rxdi input hold time 90 ns symbol parameter standard unit min. max. tc(ck) isclki input cycle time 600 ns tw(ckh) isclki input high (?h?) pulse width 300 ns tw(ckl) isclki input low (?l?) pulse width 300 ns td(c-q) istxdi output delay time 100 ns th(c-q) istxdi output hold time 0 ns tsu(d-c) isrxdi input setup time 100 ns th(c-d) isrxdi input hold time 100 ns symbol parameter standard unit min. max. tc(ck) isclk2 input cycle time 600 ns tw(ckh) isclk2 input high (?h?) pulse width 300 ns tw(ckl) isclk2 input low (?l?) pulse width 300 ns td(c-q) istxd2 output delay time 180 ns th(c-q) istxd2 output hold time 0 ns tsu(d-c) isrxd2 input setup time 150 ns th(c-d) isrxd2 input hold time 100 ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 76 of 85 timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 c unless otherwise specified) table 5.50 external interrupt inti input (edge sensitive) i = 0 to 8 (1) note: 1. int6 to int8 are provided in the 144-pin package only. symbol parameter standard unit min. max. tw(inh) inti input high (?h?) pulse width 250 ns tw(inl) inti input low (?l?) pulse width 250 ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 77 of 85 timing requirements (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 q c unless otherwise specified) table 5.51 memory expansion mode and microprocessor mode note: 1. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. insert wait states or lower the operation frequency, f(bclk), if the calculated value is negative. 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a i + b i , m = (b 2) + 1) tac1(rd-db) = 10 9 n f(bclk) - 35 [ns] (if external bus cycle is a i + b i , n = a + b) tac1(ad-db) = 10 9 m f(bclk) 2 - 35 [ns] (if external bus cycle is a i + b i , m = (b 2) - 1) tac2(rd-db) = 10 9 p f(bclk) 2 - 35 [ns] (if external bus cycle is a i + b i , p = {(a + b - 1) 2} + 1) tac2(ad-db) = symbol parameter standard unit min. max. tac1(rd-db) data input access time (rd standard) (note 1) ns tac1(ad-db) data input access time (ad standard, cs standard) (note 1) ns tac2(rd-db) data input access time (rd standar d, when accessing a space with the multiplexed bus) (note 1) ns tac2(ad-db) data input access time (ad standard, when accessing a space with the multiplexed bus) (note 1) ns tsu(db-bclk) data input setup time 30 ns tsu(rdy-bclk) rdy input setup time 40 ns tsu(hold-bclk) hold input setup time 60 ns th(rd-db) data input hold time 0 ns th(bclk-rdy) rdy input hold time 0 ns th(bclk-hold) hold input hold time 0 ns td(bclk-hlda) hlda output delay time 25 ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 78 of 85 switching characteristics (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 q c unless otherwise specified) table 5.52 memory expansion mode and micr oprocessor mode (when accessing external memory space) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 10 9 f(bclk) 2 - 20 [ns] th(wr-db) = 10 9 f(bclk) 2 - 15 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equations. 10 9 n f(bclk) 2 - 15 [ns] (if external bus cycle is a i + b i , n = (b 2) - 1) tw(wr) = 10 9 m f(bclk) - 20 [ns] (if external bus cycle is a i + b i , m = b) td(db-wr) = 3. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (3) 0 ns th(wr-ad) address output hold time (wr standard) (3) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (3) 0 ns th(wr-cs) chip-select signal output hold time (wr standard) (3) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time 0 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (3) (note 1) ns tw(wr) wr output width (note 2) ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 79 of 85 switching characteristics (vcc1 = vcc2 = 3.0 to 3.6 v, vss = 0 v, topr = -20 to 85 q c unless otherwise specified) table 5.53 memory expansion mode and microprocessor mode (when accessing external memory space with multiplexed bus) notes: 1. values, which depend on bclk frequency, can be obtained from the following equations. 10 9 f(bclk) 2 - 10 [ns] th(rd-ad) = 10 9 f(bclk) 2 - 15 [ns] th(wr-ad) = 10 9 f(bclk) 2 - 10 [ns] th(rd-cs) = 10 9 f(bclk) 2 - 10 [ns] th(wr-cs) = 10 9 f(bclk) 2 - 20 [ns] th(wr-db) = 2. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 10 9 m f(bclk) 2 - 25 [ns] (if external bus cycle is a i + b i , m = (b 2) - 1) td(db-wr) = 3. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a i + b i , n = a) td(ad-ale) = 4. values, which depend on bclk frequency and external bus cycles, can be obtained from the following equation. 10 9 n f(bclk) 2 - 20 [ns] (if external bus cycle is a i + b i , n = a) th(ale-ad) = 5. tc [ns] is added when recovery cycle is inserted. symbol parameter measurement condition standard unit min. max. td(bclk-ad) address output delay time see figure 5.2 18 ns th(bclk-ad) address output hold time (bclk standard) -3 ns th(rd-ad) address output hold time (rd standard) (5) (note 1) ns th(wr-ad) address output hold time (wr standard) (5) (note 1) ns td(bclk-cs) chip-select signal output delay time 18 ns th(bclk-cs) chip-select signal output hold time (bclk standard) -3 ns th(rd-cs) chip-select signal output hold time (rd standard) (5) (note 1) ns th(wr-cs) chip-select signal output hold time (wr standard) (5) (note 1) ns td(bclk-rd) rd signal output delay time 18 ns th(bclk-rd) rd signal output hold time -5 ns td(bclk-wr) wr signal output delay time 18 ns th(bclk-wr) wr signal output hold time 0 ns td(db-wr) data output delay time (wr standard) (note 2) ns th(wr-db) data output hold time (wr standard) (5) (note 1) ns td(bclk-ale) ale signal output delay time (bclk standard) 18 ns th(bclk-ale) ale signal output hold time (bclk standard) -2 ns td(ad-ale) ale signal output delay time (address standard) (note 3) ns th(ale-ad) ale signal output hold time (address standard) (note 4) ns tdz(rd-ad) address output float start time 8 ns vcc1 = vcc2 = 3.3 v
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 80 of 85 figure 5.7 vcc1 = vcc2 = 3.3 v timing diagram (1/4) vcc1=vcc2=3.3v taiin input tc(ta) tw(tah) tw(tal) taiout input tc(up) tw(uph) tw(upl) taiout input (counter increment/ decrement select input) taiin input (count on falling edge) taiin input (count on rising edge) th(tin-up) tsu(up-tin) in event counter mode tbiin input tc(tb) tw(tbh) tw(tbl) adtrg input tc(ad) tw(adl) clki isclki tc(ck) tw(ckh) tw(ckl) txdi istxdi th(c-q) td(c-q) rxdi isrxdi tsu(d-c) th(c-d) inti input tw(inl) tw(inh) nmi input 2 cpu clock cycles + 300 ns or more 2 cpu clock cycles + 300 ns or more ("l" width) xin input tc tw(l) tw(h) tr tf taiin input taiout input in event counter mode with two-phase pulse input tc(ta) tsu(tain-taout) tsu(tain-taout) tsu(taout-tain) tsu(taout-tain)
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 81 of 85 figure 5.8 vcc1 = vcc2 = 3.3 v timing diagram (2/4) memory expansion mode and microprocessor mode bclk rd (separate bus) wr, wrl, wrh (separate bus) rd (multiplexed bus) wr, wrl, wrh (multiplexed bus) rdy input tsu(rdy-bclk) th(bclk-rdy) hi-z tsu(hold-bclk) td(bclk-hlda) bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 measurement conditions -vcc1 = vcc2 = 3.0 to 3.6 v -input high and low voltage: vih = 2.4 v, vil = 0.6 v -output high and low voltage: voh = 1.5 v, vol = 1.5 v vcc1=vcc2=3.3v th(bclk-hold) td(bclk-hlda)
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 82 of 85 figure 5.9 vcc1 = vcc2 = 3.3 v timing diagram (3/4) vcc1=vcc2=3.3v memory expansion mode and microprocessor mode (when accessing an external memory space) notes: 1. values guaranteed only when the mcu is used stand-alone. a maximum of 35 ns is guaranteed for td(bclk-ad) + tsu(db-bclk). 2. varies with operation frequency: tac1(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) + 1) tac1(ad-db) = (tcyc x n - 35) ns.max (if external bus cycle a + b , n = a + b) read timing (1 + 1 bus cycle) write timing (1 + 1 bus cycle) notes: 3. varies with operation frequency: td(db-wr) = (tcyc x m - 20) ns.min ( if external bus cycle a + b , m = b) th(wr-db) = (tcyc / 2 - 20) ns.min th(wr-ad) = (tcyc / 2 - 15) ns.min th(wr-cs) = (tcyc / 2 - 10) ns.min tw(wr) = (tcyc / 2 x n - 15) ns.min (if external bus cycle a + b , n = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 3.0 to 3.6 v - input high and low voltage: vih = 1.5 v, vil = 0.5 v - output high and low voltage: voh = 1.5 v, vol = 1.5 v tcyc= 10 9 f(bclk) bclk csi adi bhe dbi th(bclk-cs) -3ns.min td(bclk-cs) 18ns.max tcyc td(bclk-ad) 18ns.max th(wr-ad) (3) th(bclk-wr) 0ns.min td(db-wr) (3) th(bclk-ad) -3ns.min td(bclk-wr) 18ns.max tw(wr) (3) th(wr-db) (3) th(wr-cs) (3) wr,wrl,wrh bclk csi adi bhe rd dbi th(bclk-cs) -3ns.min th(rd-cs) 0ns.min td(bclk-cs) 18ns.max (1) tcyc td(bclk-ad) 18ns.max (1) 18ns.max td(bclk-rd) th(rd-ad) 0ns.min th(bclk-rd) -5ns.min tac1(rd-db) (2) tac1(ad-db) (2) hi-z th(rd-db) 0ns.min tsu(db-bclk) 30ns.min (1) th(bclk-ad) -3ns.min
m32c/87 group (m32c/87, m32c/87a, m32c /87b) 5. electrical characteristics rej03b0127-0151 rev.1.51 jul 31, 2008 page 83 of 85 figure 5.10 vcc1 = vcc2 = 3.3 v timing diagram (4/4) bclk csi adi bhe rd ale td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (1) th(ale-ad) (1) tdz(rd-ad) 8ns.max tac2(rd-db) (1) th(bclk-cs) -3ns.min th(rd-db) 0ns.min th(bclk-ad) -3ns.min td(bclk-ad) 18ns.max adi /dbi td(bclk-rd) 18ns.max tac2(ad-db) (1) th(bclk-rd) -5ns.min th(rd-ad) (1) tcyc address notes: 1. varies with operation frequency: td(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(ale-ad) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(rd-ad) = (tcyc / 2 - 10) ns.min, th(rd-cs) = (tcyc / 2 - 10) ns.min tac2(rd-db) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b , m = (b x 2) - 1) tac2(ad-db) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b , p = {(a + b - 1) x 2} + 1) notes: 1. varies with operation frequency: td(ad-ale) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(ale-ad) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b , n = a) th(wr-ad) = (tcyc / 2 - 15) ns.min, th(wr-cs) = (tcyc / 2 - 10) ns.min th(wr-db) = (tcyc / 2 - 20) ns.min td(db-wr) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b , m = (b x 2) - 1) measurement conditions: - vcc1 = vcc2 = 3.0 to 3.6 v - input high and low voltage vih = 1.5 v, vil = 0.5 v - output high and low voltage voh = 1.5 v, vol = 1.5 v address vcc1=vcc2=3.3v memory expansion mode and microprocessor mode (when accessing an external memory space with the multiplexed bus) read timing (2 + 2 bus cycle) tcyc= 10 9 f(bclk) bclk csi adi bhe wr,wrl,wrh write timing (2 + 2 bus cycle) td(bclk-ale) 18ns.max th(bclk-ale) -2ns.min td(bclk-cs) 18ns.max td(ad-ale) (2) th(ale-ad) (2) td(db-wr) (2) th(wr-cs) (2) td(bclk-ad) 18ns.max td(bclk-wr) 18ns.max th(bclk-wr) 0ns.min tcyc address data output th(wr-db) (2) adi /dbi ale address th(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min th(rd-cs) (1) data input tsu(db-bclk) 30ns.min th(wr-ad) (2)
m32c/87 group (m32c/87, m32c/87a, m32c /87b) appendix 1. package dimensions rej03b0127-0151 rev.1.51 jul 31, 2008 page 84 of 85 appendix 1. package dimensions terminal cross section b 1 c 1 b p c 1.0 0.125 0.20 1.25 1.25 0.08 0.20 0.145 0.09 0.27 0.22 0.17 max nom min dimension in millimeters symbol reference 20.1 20.0 19.9 d 20.1 20.0 19.9 e 1.4 a 2 22.2 22.0 21.8 22.2 22.0 21.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 p-lqfp144-20x20-0.50 1.2g mass[typ.] 144p6q-a / fp-144l / fp-144lv plqp0144ka-a renesas code jeita package code previous code f 1 36 37 72 73 108 109 144 * 1 * 2 * 3 x index mark y h e e d h d b p z d z e detail f c a l a 1 a 2 l 1 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. e terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e
m32c/87 group (m32c/87, m32c/87a, m32c /87b) appendix 1. package dimensions rej03b0127-0151 rev.1.51 jul 31, 2008 page 85 of 85 0.8 0.5 0.825 0.575 z e z d b p a 1 h e h d y 0.10 e 0.65 c 0 10 l 0.4 0.6 0.8 0 0.1 0.2 a 3.05 16.5 16.8 17.1 22.5 22.8 23.1 a 2 2.8 e 13.8 14.0 14.2 d 19.8 20.0 20.2 reference symbol dimension in millimeters min nom max 0.25 0.3 0.4 0.13 0.15 0.2 p-qfp100-14x20-0.65 1.6g mass[typ.] 100p6s-a prqp0100jb-a renesas code jeita package code previous code y index mark 100 81 80 51 50 31 30 1 f * 2 * 1 * 3 z e z d e b p a h d d e h e c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2.
a - 1 revision history m32c/87 group datasheet rev. date description page summary 0.50 dec.16, 04 ? new document 1.00 jul.14, 05 ? ? ? m32c/87a and m32c/87b added package code changed: 144p6q-a to plqp0144ka-a, 100p6q-a to plqp0100kb-a, 100p6s-a to prqp0100jb-a ?low voltage detection reset? changed to ?brown-out detection reset? 2 3 4 7 8 11 12 13 17 overview ? table 1.2 m32c/87 group performance (144-pin package) m32c/87a and m32c/87b performance added to the can module performance; power consumption performance released ? table 1.2 m32c/87 group performance (100-pin package) m32c/87a and m32c/87b performance added to the can module performance; power consumption performance released ? figure 1.1 m32c/87 group block diagram note 4 deleted; note 5 added ? figure 1.3 pin assignment for 144-pin package note 15 added ? table 1.4 pin characteristics for 144-pin package note 1 added ? figure 1.4 pin assignment for 100-pin package note 19 added ? figure 1.5 pin assignment for 100-pin package note 15 added ? table 1.5 pin characteristics for 100-pin package note 1 added ? table 1.6 pin description note 2 added 22 memory ? figure 3.1 memory map note 3 changed 26 26 27 to 30 27 27 29 32 to 37 40 41 42 42 43 44 45 special function register (sfr) ? the rlvl register value after reset modified ? the iio0ir to iio11ir registers value after reset modified ? name of the registers assosiated to intelligent i/o changed ? the g0rb register value after reset modified ? the g1bcr0 and g1bcr1 regist ers value after reset modified ? the g0cr register value after reset modified ? note added to the ca n-associated registers ? the tcspr register value after reset modified; note 1 added ? the ad00 register value after reset modified ? the psc register value after reset modified ? the ps2 register value after reset modified ? the pcr register value after reset modified ? the psd1 register value after reset modified ? the pcr register value after reset modified 48 49 50 52 54 electrical characteristics ? table 5.2 electrical characteristics parameter f (bclk) and its values added; min. and max. values for f(ring) added ? table 5.3 electrical characteristics v oh values modified ; r pullup value modified ? table 5.3 electrical characteristics (continued) measurement condition and standard values for icc added and some released ? table 5.6 flash memory version electrical characteristics word program time and lock bit program time values modified; parameter all- unlocked-block-erase time deleted; note 1 deleted ? table 5.10 memory expansion mode and microprocessor mode tac1(rd-db) expression on note 1 modified; tac2(rd-db) expression on note 1 added
a - 2 revision history m32c/87 group datasheet 57 58 60 61 62 64 65 66 69 70 71 72 73 electrical characteristics ? table 5.22 memory expansion mode and microprocessor mode th(wr- db) expression on note 1 modified ? table 5.23 memory expansion mode and microprocessor mode th(wr- db) expression on note 1 modified; th(ale-ad) expression on note 4 modified ? figure 5.3 vcc1=vcc2= 5v timing diagram (1) tac1(rd-db) expression on note 2 modified; th(wr-db) and tw(er) expressions on note 3 modified; tcyc expression added ? figure 5.4 vcc1=vcc2= 5v timing diagram (2) tac2(rd-db) and tac2(ad- db) expressions on note 1 modified; th(ale-ad) expressions on notes 1 and 2 modified; td(db-wr) expression on note 2 modified; tcyc expression added ? figure 5.5 vcc1=vcc2=5v timing diagram (3) nmi input diagram added ? table 5.24 electri cal characteristics v oh values changed ; r pullup and icc values modified ? table 5.25 a/d conversion characteristics tconv value modified ? table 5.28 memory expansion mode and microprocessor mode tac1(rd-db) expression on note 1 modified; tac2(rd-db) expression on note 1 added ? table 5.40 memory expansion mode and microprocessor mode th (bclk-ad), th (bclk-cs) and th (bclk-rd) values modified; th (wr-ad) expression on note 1 modified ? table 5.41 memory expansion mode and microprocessor mode th (bclk-ad), th (bclk-cs) and th (bclk-rd) values modified; th (wr-ad) expression on note 1 modified; th (ale-ad) expression on note 4 modified ? figure 5.7 vcc1=vcc2=3. 3v timing diagram (1) th (bclk-ad), th (bclk- cs) and th (bclk-rd) values modified; tac 1(ad-db) expression on note 2 modified; th (wr-db) , th (wr-ad) and tw (wr) expression on note 3 modified; tcyc expression added ? figure 5.8 vcc1=vcc2=3. 3v timing diagram (2) tac 2(rd-db) and tac 1(ad-db) expressions on note 1 modified; th (ale-ad) expressions on notes 1 and 2 modified; td (wr-ad) , td (db-wr) and th (wr-db) expressions on note 2 modified; tcyc expression added ? figure 5.9 vcc1=vcc2=3. 3v timing diagram (3) nmi input diagram added 1.01 aug. 29, 05 17 overview ? tables 1.6 pin description intelligent i/o functions modified 29 29 special function register (sfr) ? the g1bcr0 register value after reset modified ? the g1bcr1 register value after reset modified 49 electrical characteristics ? table 5.3 electrical characteristics i cc standard value modified rev. date description page summary
a - 3 revision history m32c/87 group datasheet 1.50 oct 20, 2007 all all in this manual ? descriptions and formats unified ? notation of numbers changed (e.g. 00 2 00b, ff 16 ffh) ? notation of pin name changed (e.g. rtp00 rtp_0, a15(/d15) [a15/d15]) ? [term changed] serial i/o serial interface clock synchronous serial i/o mode clock synchronous mode clock asynchronous serial i/o mode clock asynchronous mode clock synchronous variable length variable data length clock synchronous voltage detection circuit power supply voltage detection function low voltage detection interrupt vdet4 detection interrupt brown-out detection reset vdet3 detection function 1 2 2-5 8 6-7 9, 14, 15 11,17 19-22 overview ? header single-chip 16/32-bi t cmos microcomputer renesas mcu ? 1.1 features title added; 1.1 applications changed to 1.1.1 applications ? 1.2 performance overview changed to 1.1.2 specifications ? tables 1.1 to 1.4 structure, descriptions in specification field, note, and value partially revised or deleted ? real-time port item deleted; rom correction function item added ? 1.3 block diagram moved following the 1.2 product list ? 1.2 product list tables revised; note 1 added ? figures 1.3 to 1.5 arrows for vss and vcc deleted; notes partially modified ? tables 1.9 and 1.13 clkout pin moved from bus control pin column to control pin column ? tables 1.15 to 1.19 descriptions revised; note 1 added 26 memory ? text partially modified 34-39 45 27 34 41 42 sfr ? tables 4.8 to 4.13 note ?set the pm13 bit in the pm1 register to 1 (2 wait states for sfr area) before accessing the can-associated registers.? added ? table 4.19 the psl5 register added to the address field of 03bbh item; the psl7 register added to the address field of 03bfh item ? [register names changed] 002fh low voltage detection interrupt register vdet4 detection interrupt register 01c1h uart5 bit rate register uart5 baud rate register 01c9h uart6 bit rate register uart6 baud rate register 01d0h uart5, uart6 transmit/r eceive control register 2 uart5, uart6 transmit/receive control register 01dbh to 01d8h pulse output data register rtp output buffer register 0303h to 0302h timer a1-1 register timer a11 register 0305h to 0304h timer a2-1 register timer a21 register 0307h to 0306h timer a4-1 register timer a41 register 0340h count start flag count start register 0341h clock prescaler reset flag clock prescaler reset register rev. date description page summary
a - 4 revision history m32c/87 group datasheet 42 27 27 29 31 31 32 34 34 44 sfr ? [register names changed] 0342h one-shot start flag one-shot start register 0344h up-down flag up/down select register ? [value after reset changed] 000fh wdc 000x xxx 2 00xx xxxxb 002fh d4int 00 16 xx00 0000b 007bh iio6ic xx00 x000 2 xxxx x000b 00efh g0cr xx00 x011 2 0000 x011b 00feh g0irf 00 16 0000 xxxxb 013eh g1irf 00 16 0000 xxxxb 01c7h to 01c6h u5rb xxxx xxxx xxxx 0xxx 2 xxxxh 01cfh to 01ceh u6rb xxxx xxxx xxxx 0xxx 2 xxxxh 038fh to 0382h ad07 to ad01 xxxx 16 00xxh 47 50-53 50 51,69 53,71 54 54,55 56,73 58,74 59 60 61 62-63 65-68 69-72 75 76 77 78-79 80-83 electrical characteristics ? [term changed] low voltage reset hardware reset 2 low voltage detection vdet3 and vdet4 detection circuit ? table 5.1 description in condition field of pd (power consumption) partially modified ? tables 5.2 to 5.9 f(bclk) is changed to f(cpu) ? table 5.4 description added in parameter field of f(cpu); f(vco) added ? tables 5.5 to 5.7 and tables 5.31 to 5.33 description in xcout and hysteresis in parameter fields partially modified ? table 5.7 and 5.33 structure and standard values revised; items in measurement condition and note added ? table 5.8 description in parameter field and note partially modified ? table 5.9 and 5.10 description in parameter field and note partially modified ? tables 5.11 and 5.36 description in parameter field and standard value partially modified ? tables 5.19 and 5.42 added ? table 5.24 values revised; table 5.25 and 5.26 added ? table 5.27 titles modified; note added ? table 5.28 moved to the last table in timing requirements ? table 5.29 note 3 added; table 26.30 note 5 added ? figures 5.3 to 5.6 order rearranged; measurement condition modified ? table 5.31 to 5.35 f(bclk) revised to f(cpu) ? table 5.47 values revised; table5.48 and 5.49 added ? table 5.50 titles modified; note added ? table 5.51 table moved to the last table in timing requirements ? table 5.52 note 3 added ; table 5.53 note 5 added ? figures 5.7 to 5.10 order rearranged 1.51 jul 31, 2008 ? all in this manual [description modified] ? title of group tables ?(current table number / total tables)? added 19 21 overview ? 1.5 pin descriptions chapter and table title changed to pin functions ? table 1.17 supply voltage for an0_0 to an0_7, an2_0 to an2_7 modified rev. date description page summary
all trademarks and registered trademarks are t he property of their respective owners. iebus is a registered trademark of nec electronics corporation. a - 5 revision history m32c/87 group datasheet 46 special function registers (sfrs) ? table 4.20 a value of after reset co lumn in 03ffh modified rev. date description page summary
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